ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_usb_regs.h
Go to the documentation of this file.
1
68
69#pragma once
70
71#ifdef __cplusplus
72extern "C" {
73#endif
74
75#include <stddef.h>
76#include <stdint.h>
77
78#include "ra8_attributes.h"
79
87typedef enum : uintptr_t {
88#ifdef RA8_PERIPH_NS_ALIAS
89 /* TrustZone Non-secure build (two-project NS image, #96): reach the
90 * controllers through the IDAU bit[28]=1 Non-secure alias (HUM "PSCU_NS =
91 * 0x5020_4000" pattern, +0x1000_0000) so the SAU NS peripheral region
92 * (0x5000_0000-0xDFFF_FFFF) permits the access. The Secure side marks USBFS0
93 * Non-secure in PSARB (PSARB11) so the alias actually responds. */
94 k_ra8_usb_fs0_base_addr = 0x50250000UL,
95 k_ra8_usb_hs0_base_addr = 0x50351000UL,
96#else
97 k_ra8_usb_fs0_base_addr = 0x40250000UL,
98 k_ra8_usb_hs0_base_addr = 0x40351000UL,
99#endif
101
115
126typedef struct {
127 volatile uint16_t SYSCFG;
128 volatile uint16_t BUSWAIT;
129 volatile uint16_t SYSSTS0;
130 volatile uint16_t _r0;
131 volatile uint16_t DVSTCTR0;
132 volatile uint16_t _r1[k_ra8_usb_pad_5];
133 volatile uint16_t CFIFO;
134 volatile uint16_t _r2;
135 volatile uint16_t D0FIFO;
136 volatile uint16_t _r3;
137 volatile uint16_t D1FIFO;
138 volatile uint16_t _r4;
139 volatile uint16_t CFIFOSEL;
140 volatile uint16_t CFIFOCTR;
141 volatile uint16_t _r5[k_ra8_usb_pad_2];
142 volatile uint16_t D0FIFOSEL;
143 volatile uint16_t D0FIFOCTR;
144 volatile uint16_t D1FIFOSEL;
145 volatile uint16_t D1FIFOCTR;
146 volatile uint16_t INTENB0;
147 volatile uint16_t INTENB1;
148 volatile uint16_t _r6;
149 volatile uint16_t BRDYENB;
150 volatile uint16_t NRDYENB;
151 volatile uint16_t BEMPENB;
152 volatile uint16_t SOFCFG;
153 volatile uint16_t _r7;
154 volatile uint16_t INTSTS0;
155 volatile uint16_t INTSTS1;
156 volatile uint16_t _r8;
157 volatile uint16_t BRDYSTS;
158 volatile uint16_t NRDYSTS;
159 volatile uint16_t BEMPSTS;
160 volatile uint16_t FRMNUM;
161 volatile uint16_t _r9;
162 volatile uint16_t USBADDR;
163 volatile uint16_t _ra;
164 volatile uint16_t USBREQ;
165 volatile uint16_t USBVAL;
166 volatile uint16_t USBINDX;
167 volatile uint16_t USBLENG;
168 volatile uint16_t DCPCFG;
169 volatile uint16_t DCPMAXP;
170 volatile uint16_t DCPCTR;
171 volatile uint16_t _rb;
172 volatile uint16_t PIPESEL;
173 volatile uint16_t _rc;
174 volatile uint16_t PIPECFG;
175 volatile uint16_t PIPEBUF;
176 volatile uint16_t PIPEMAXP;
177 volatile uint16_t PIPEPERI;
178 volatile uint16_t PIPECTR[k_ra8_usb_pipectr_count];
180
230
239typedef enum : uint16_t {
242
257static_assert(sizeof(r_usb_regs_t) == (size_t)k_ra8_usb_window_bytes,
258 "r_usb_regs_t window size must be 0x082 bytes (PIPECTR[9] end)");
259
260static_assert(offsetof(r_usb_regs_t, SYSCFG) == (size_t)k_ra8_usb_off_syscfg, "SYSCFG offset");
261static_assert(offsetof(r_usb_regs_t, BUSWAIT) == (size_t)k_ra8_usb_off_buswait, "BUSWAIT offset");
262static_assert(offsetof(r_usb_regs_t, SYSSTS0) == (size_t)k_ra8_usb_off_syssts0, "SYSSTS0 offset");
263static_assert(offsetof(r_usb_regs_t, DVSTCTR0) == (size_t)k_ra8_usb_off_dvstctr0,
264 "DVSTCTR0 offset");
265static_assert(offsetof(r_usb_regs_t, CFIFO) == (size_t)k_ra8_usb_off_cfifo, "CFIFO offset");
266static_assert(offsetof(r_usb_regs_t, D0FIFO) == (size_t)k_ra8_usb_off_d0fifo, "D0FIFO offset");
267static_assert(offsetof(r_usb_regs_t, D1FIFO) == (size_t)k_ra8_usb_off_d1fifo, "D1FIFO offset");
268static_assert(offsetof(r_usb_regs_t, CFIFOSEL) == (size_t)k_ra8_usb_off_cfifosel,
269 "CFIFOSEL offset");
270static_assert(offsetof(r_usb_regs_t, CFIFOCTR) == (size_t)k_ra8_usb_off_cfifoctr,
271 "CFIFOCTR offset");
272static_assert(offsetof(r_usb_regs_t, D0FIFOSEL) == (size_t)k_ra8_usb_off_d0fifosel,
273 "D0FIFOSEL offset");
274static_assert(offsetof(r_usb_regs_t, D0FIFOCTR) == (size_t)k_ra8_usb_off_d0fifoctr,
275 "D0FIFOCTR offset");
276static_assert(offsetof(r_usb_regs_t, D1FIFOSEL) == (size_t)k_ra8_usb_off_d1fifosel,
277 "D1FIFOSEL offset");
278static_assert(offsetof(r_usb_regs_t, D1FIFOCTR) == (size_t)k_ra8_usb_off_d1fifoctr,
279 "D1FIFOCTR offset");
280static_assert(offsetof(r_usb_regs_t, INTENB0) == (size_t)k_ra8_usb_off_intenb0, "INTENB0 offset");
281static_assert(offsetof(r_usb_regs_t, INTENB1) == (size_t)k_ra8_usb_off_intenb1, "INTENB1 offset");
282static_assert(offsetof(r_usb_regs_t, BRDYENB) == (size_t)k_ra8_usb_off_brdyenb, "BRDYENB offset");
283static_assert(offsetof(r_usb_regs_t, NRDYENB) == (size_t)k_ra8_usb_off_nrdyenb, "NRDYENB offset");
284static_assert(offsetof(r_usb_regs_t, BEMPENB) == (size_t)k_ra8_usb_off_bempenb, "BEMPENB offset");
285static_assert(offsetof(r_usb_regs_t, SOFCFG) == (size_t)k_ra8_usb_off_sofcfg, "SOFCFG offset");
286static_assert(offsetof(r_usb_regs_t, INTSTS0) == (size_t)k_ra8_usb_off_intsts0, "INTSTS0 offset");
287static_assert(offsetof(r_usb_regs_t, INTSTS1) == (size_t)k_ra8_usb_off_intsts1, "INTSTS1 offset");
288static_assert(offsetof(r_usb_regs_t, BRDYSTS) == (size_t)k_ra8_usb_off_brdysts, "BRDYSTS offset");
289static_assert(offsetof(r_usb_regs_t, NRDYSTS) == (size_t)k_ra8_usb_off_nrdysts, "NRDYSTS offset");
290static_assert(offsetof(r_usb_regs_t, BEMPSTS) == (size_t)k_ra8_usb_off_bempsts, "BEMPSTS offset");
291static_assert(offsetof(r_usb_regs_t, FRMNUM) == (size_t)k_ra8_usb_off_frmnum, "FRMNUM offset");
292static_assert(offsetof(r_usb_regs_t, USBADDR) == (size_t)k_ra8_usb_off_usbaddr, "USBADDR offset");
293static_assert(offsetof(r_usb_regs_t, USBREQ) == (size_t)k_ra8_usb_off_usbreq, "USBREQ offset");
294static_assert(offsetof(r_usb_regs_t, USBVAL) == (size_t)k_ra8_usb_off_usbval, "USBVAL offset");
295static_assert(offsetof(r_usb_regs_t, USBINDX) == (size_t)k_ra8_usb_off_usbindx, "USBINDX offset");
296static_assert(offsetof(r_usb_regs_t, USBLENG) == (size_t)k_ra8_usb_off_usbleng, "USBLENG offset");
297static_assert(offsetof(r_usb_regs_t, DCPCFG) == (size_t)k_ra8_usb_off_dcpcfg, "DCPCFG offset");
298static_assert(offsetof(r_usb_regs_t, DCPMAXP) == (size_t)k_ra8_usb_off_dcpmaxp, "DCPMAXP offset");
299static_assert(offsetof(r_usb_regs_t, DCPCTR) == (size_t)k_ra8_usb_off_dcpctr, "DCPCTR offset");
300static_assert(offsetof(r_usb_regs_t, PIPESEL) == (size_t)k_ra8_usb_off_pipesel, "PIPESEL offset");
301static_assert(offsetof(r_usb_regs_t, PIPECFG) == (size_t)k_ra8_usb_off_pipecfg, "PIPECFG offset");
302static_assert(offsetof(r_usb_regs_t, PIPEBUF) == (size_t)k_ra8_usb_off_pipebuf, "PIPEBUF offset");
303static_assert(offsetof(r_usb_regs_t, PIPEMAXP) == (size_t)k_ra8_usb_off_pipemaxp,
304 "PIPEMAXP offset");
305static_assert(offsetof(r_usb_regs_t, PIPEPERI) == (size_t)k_ra8_usb_off_pipeperi,
306 "PIPEPERI offset");
307static_assert(offsetof(r_usb_regs_t, PIPECTR) == (size_t)k_ra8_usb_off_pipectr,
308 "PIPECTR base offset");
309static_assert(sizeof(((r_usb_regs_t*)0)->PIPECTR) ==
310 ((size_t)k_ra8_usb_pipectr_count * sizeof(uint16_t)),
311 "PIPECTR array spans PIPE1..PIPE9 (9 * 2 bytes)");
312
315static inline volatile r_usb_regs_t* ra8_usb_fs(void)
316{
317 return (volatile r_usb_regs_t*)k_ra8_usb_fs0_base_addr;
318}
319
322static inline volatile r_usb_regs_t* ra8_usb_hs(void)
323{
324 return (volatile r_usb_regs_t*)k_ra8_usb_hs0_base_addr;
325}
326
327/* =============================================================================
328 * USBHS-only register offsets (HUM Ch 37 "USB 2.0 High-Speed Module")
329 * =============================================================================
330 */
331
347typedef enum : uint16_t {
352
355static inline volatile uint16_t* ra8_usbhs_pllsta(void)
356{
357 return (volatile uint16_t*)(k_ra8_usb_hs0_base_addr + (uintptr_t)k_ra8_usbhs_off_pllsta);
358}
359
362static inline volatile uint16_t* ra8_usbhs_physet(void)
363{
364 return (volatile uint16_t*)(k_ra8_usb_hs0_base_addr + (uintptr_t)k_ra8_usbhs_off_physet);
365}
366
369static inline volatile uint16_t* ra8_usbhs_lpsts(void)
370{
371 return (volatile uint16_t*)(k_ra8_usb_hs0_base_addr + (uintptr_t)k_ra8_usbhs_off_lpsts);
372}
373
389
394typedef enum : uint16_t {
397
402typedef enum : uint16_t {
405
415typedef enum : uint16_t {
418
419/* =============================================================================
420 * SYSCFG bit positions (HUM Ch 36.2.1 / Ch 37.2.1)
421 * =============================================================================
422 */
423
437
438/* =============================================================================
439 * INTENB0 / INTSTS0 bit positions (HUM Ch 36.2.10 / Ch 36.2.14)
440 * =============================================================================
441 */
442
457
475
480typedef enum : uint16_t {
493
504
512typedef enum : uint16_t {
517 /* Suspend flag is bit 6 on BOTH controllers. USBHS additionally
518 * reports VBUS presence in INTSTS0 bit 7 -- strip it before
519 * comparing DVSQ values (observed live: bit 7 tracks the cable). */
522
527typedef enum : uint16_t {
528 k_ra8_ctsq_idle = 0x0000U,
529 k_ra8_ctsq_rdds = 0x0001U,
530 k_ra8_ctsq_rdss = 0x0002U,
531 k_ra8_ctsq_wrds = 0x0003U,
532 k_ra8_ctsq_wrss = 0x0004U,
533 k_ra8_ctsq_wrnd = 0x0005U,
534 k_ra8_ctsq_sqer = 0x0006U,
536
537/* =============================================================================
538 * DCPCTR bit positions (HUM Ch 36.2.21)
539 * =============================================================================
540 */
541
558
568typedef enum : uint8_t {
571
577typedef enum : uint16_t {
578 k_ra8_pid_nak = 0x0000U,
579 k_ra8_pid_buf = 0x0001U,
580 k_ra8_pid_stall = 0x0002U,
581 k_ra8_pid_mask = 0x0003U,
583
584/* =============================================================================
585 * CFIFOSEL / DnFIFOSEL bit positions (HUM Ch 36.2.7)
586 * =============================================================================
587 */
588
606
607/* =============================================================================
608 * CFIFOCTR / DnFIFOCTR bit positions (HUM Ch 36.2.8)
609 * =============================================================================
610 */
611
616typedef enum : uint16_t {
622
623/* =============================================================================
624 * USBADDR field (HUM Ch 36.2.16)
625 * =============================================================================
626 */
627
632typedef enum : uint16_t {
635
636/* =============================================================================
637 * PIPECFG fields (HUM Ch 36.2.24)
638 * =============================================================================
639 */
640
656
657/* =============================================================================
658 * PIPEBUF fields (HUM Ch 37.2.35)
659 * =============================================================================
660 */
661
678
679/* =============================================================================
680 * PIPECTR bit positions (HUM Ch 36.2.27)
681 * =============================================================================
682 */
683
699
700#ifdef __cplusplus
701}
702#endif
Annotation-attribute framework macros for ra8-firmware.
#define RA8_HW_REGISTER_ACCESS
Mark an MMIO accessor function (returns volatile register pointer).
static volatile uint16_t * ra8_usbhs_lpsts(void)
Get pointer to USBHS LPSTS register.
ra8_usb_intsts1_bit_t
INTSTS1 / INTENB1 host-mode bit positions (HUM Ch 36.2.11/15).
@ k_ra8_int1_bit_eoferr
EOF error detected.
@ k_ra8_int1_bit_dtch
Device detach detected.
@ k_ra8_int1_bit_attch
Device attach detected.
@ k_ra8_int1_bit_bchg
Bus change.
@ k_ra8_int1_bit_sign
SETUP transaction failed (3x).
@ k_ra8_int1_bit_sack
SETUP transaction ACKed.
@ k_ra8_int1_bit_ovrcr
Overcurrent input change.
ra8_usb_pipectr_bit_t
PIPECTR bit positions / fields used by the driver.
@ k_ra8_pipectr_sqset
Toggle set.
@ k_ra8_pipectr_inbufm
IN buffer monitor.
@ k_ra8_pipectr_aclrm
Auto buffer clear mode.
@ k_ra8_pipectr_pbusy
Pipe busy (read-only).
@ k_ra8_pipectr_sqclr
Toggle clear.
@ k_ra8_pipectr_bsts
Buffer status.
@ k_ra8_pipectr_sqmon
Toggle monitor.
@ k_ra8_pipectr_atrepm
Auto response mode.
@ k_ra8_pipectr_pid_mask
PID[1:0] response field.
ra8_usbhs_lpsts_bit_t
LPSTS bit positions (HUM Ch 37 "LPSTS" register).
@ k_ra8_lpsts_suspendm
b14: UTMI SuspendM (1=run).
ra8_usbhs_pllsta_bit_t
PLLSTA bit positions (HUM Ch 37 "PLLSTA" register).
@ k_ra8_pllsta_plllock
b0 : PHY PLL locked flag.
ra8_usbhs_physet_bit_t
PHYSET bit positions and masks (HUM Ch 37 "PHYSET" register).
@ k_ra8_physet_clksel
b5-4: input clock select mask.
@ k_ra8_physet_hseb
b15 : CL-only mode.
@ k_ra8_physet_pllreset
b1 : PHY PLL reset.
@ k_ra8_physet_clksel_48
b5-4 = 01b: 48 MHz reference.
@ k_ra8_physet_clksel_12
b5-4 = 00b: 12 MHz reference.
@ k_ra8_physet_repsel_16
b9-8: 16-cycle terminator.
@ k_ra8_physet_clksel_20
b5-4 = 10b: 20 MHz reference.
@ k_ra8_physet_clksel_24
b5-4 = 11b: 24 MHz reference.
@ k_ra8_physet_dirpd
b0 : PHY power-down (1=PD).
ra8_usb_pid_t
Response PID values written into the low two bits of DCPCTR / PIPECTR.
@ k_ra8_pid_buf
BUF response (transmit/receive).
@ k_ra8_pid_nak
NAK response.
@ k_ra8_pid_mask
PID[1:0] field mask.
@ k_ra8_pid_stall
STALL response.
ra8_usb_syscfg_bit_t
SYSCFG bit positions.
@ k_ra8_syscfg_bit_dprpu
D+ pull-up enable (device).
@ k_ra8_syscfg_bit_usbe
USB module enable.
@ k_ra8_syscfg_bit_cnen
Single-end receiver enable.
@ k_ra8_syscfg_bit_hse
HS enable (HS instance only).
@ k_ra8_syscfg_bit_drpd
D+/D- pull-down (host).
@ k_ra8_syscfg_bit_dcfm
1 = host mode, 0 = device.
@ k_ra8_syscfg_bit_scke
USB clock enable.
ra8_usb_intenb0_mask_t
INTENB0 aggregate masks (HUM Ch 36.2.10 p 1980).
@ k_ra8_int0_full_mask
Device-mode event mask: BRDY | NRDY | BEMP | CTRT | DVST | VBSE.
static volatile uint16_t * ra8_usbhs_physet(void)
Get pointer to USBHS PHYSET register.
static volatile uint16_t * ra8_usbhs_pllsta(void)
Get pointer to USBHS PLLSTA register (read-only).
ra8_usb_offset_t
Byte offsets of the named USB register fields within r_usb_regs_t.
@ k_ra8_usb_off_brdyenb
BRDYENB : BRDY Enable.
@ k_ra8_usb_off_d1fifo
D1FIFO : DMA FIFO 1 port.
@ k_ra8_usb_off_pipecfg
PIPECFG : Selected pipe cfg.
@ k_ra8_usb_off_pipectr
PIPECTR : PIPE1..9 control.
@ k_ra8_usb_off_syssts0
SYSSTS0 : System status 0.
@ k_ra8_usb_off_usbleng
USBLENG : USB request wLength.
@ k_ra8_usb_off_dvstctr0
DVSTCTR0 : Device state ctrl.
@ k_ra8_usb_off_d0fifosel
D0FIFOSEL : DMA FIFO 0 select.
@ k_ra8_usb_off_usbindx
USBINDX : USB request wIndex.
@ k_ra8_usb_off_d0fifoctr
D0FIFOCTR : DMA FIFO 0 control.
@ k_ra8_usb_off_nrdysts
NRDYSTS : NRDY Status.
@ k_ra8_usb_off_bempenb
BEMPENB : BEMP Enable.
@ k_ra8_usb_off_usbaddr
USBADDR : USB address.
@ k_ra8_usb_off_pipebuf
PIPEBUF : Selected pipe buf.
@ k_ra8_usb_off_usbval
USBVAL : USB request wValue.
@ k_ra8_usb_off_d1fifosel
D1FIFOSEL : DMA FIFO 1 select.
@ k_ra8_usb_off_cfifosel
CFIFOSEL : Control FIFO select.
@ k_ra8_usb_off_d1fifoctr
D1FIFOCTR : DMA FIFO 1 control.
@ k_ra8_usb_off_d0fifo
D0FIFO : DMA FIFO 0 port.
@ k_ra8_usb_off_bempsts
BEMPSTS : BEMP Status.
@ k_ra8_usb_off_intsts1
INTSTS1 : Interrupt Status 1.
@ k_ra8_usb_off_intenb1
INTENB1 : Interrupt Enable 1.
@ k_ra8_usb_off_pipeperi
PIPEPERI : Selected pipe period.
@ k_ra8_usb_off_dcpmaxp
DCPMAXP : DCP max packet.
@ k_ra8_usb_off_nrdyenb
NRDYENB : NRDY Enable.
@ k_ra8_usb_off_cfifo
CFIFO : Control FIFO port.
@ k_ra8_usb_off_dcpctr
DCPCTR : DCP control.
@ k_ra8_usb_off_intsts0
INTSTS0 : Interrupt Status 0.
@ k_ra8_usb_off_usbreq
USBREQ : USB request type.
@ k_ra8_usb_off_pipemaxp
PIPEMAXP : Selected pipe maxp.
@ k_ra8_usb_off_brdysts
BRDYSTS : BRDY Status.
@ k_ra8_usb_off_pipesel
PIPESEL : Pipe window select.
@ k_ra8_usb_off_cfifoctr
CFIFOCTR : Control FIFO control.
@ k_ra8_usb_off_intenb0
INTENB0 : Interrupt Enable 0.
@ k_ra8_usb_off_dcpcfg
DCPCFG : DCP configuration.
@ k_ra8_usb_off_buswait
BUSWAIT : CPU bus wait.
@ k_ra8_usb_off_sofcfg
SOFCFG : SOF Output Config.
@ k_ra8_usb_off_syscfg
SYSCFG : System config.
@ k_ra8_usb_off_frmnum
FRMNUM : Frame number.
ra8_usb_fifoctr_field_t
CFIFOCTR / DxFIFOCTR field masks.
@ k_ra8_fifoctr_frdy
FIFO ready.
@ k_ra8_fifoctr_bclr
Buffer clear.
@ k_ra8_fifoctr_dtln
Data length (write-bytes-rem).
@ k_ra8_fifoctr_bval
Buffer valid.
ra8_usb_dcpctr_bit_t
DCPCTR bit positions used by the device-mode driver.
@ k_ra8_dcpctr_bit_sureq
Send USB request (host mode).
@ k_ra8_dcpctr_bit_sqset
Sequence toggle set.
@ k_ra8_dcpctr_bit_pbusy
Pipe busy.
@ k_ra8_dcpctr_bit_bsts
Buffer status.
@ k_ra8_dcpctr_bit_sqclr
Sequence toggle clear.
@ k_ra8_dcpctr_bit_sqmon
Sequence toggle monitor.
@ k_ra8_dcpctr_bit_ccpl
Control transfer end enable.
@ k_ra8_dcpctr_bit_sureqclr
SUREQ clear (USBHS host only).
@ k_ra8_dcpctr_bit_pid_hi
PID[1].
@ k_ra8_dcpctr_bit_pid_lo
PID[0] (NAK / BUF / STALL).
ra8_usb_pipebuf_field_t
PIPEBUF field masks / shifts.
@ k_ra8_pipebuf_block_bytes
Each buffer block is 64 bytes.
@ k_ra8_pipebuf_bufsize_shift
RA8 pipebuf bufsize shift.
@ k_ra8_pipebuf_bufnmb_mask
RA8 pipebuf bufnmb mask.
@ k_ra8_pipebuf_bufsize_mask
RA8 pipebuf bufsize mask.
ra8_usb_dcpcfg_bit_t
DCPCFG bit positions used by the control-transfer engine.
@ k_ra8_dcpcfg_bit_dir
Transfer direction (host: 0 = IN, 1 = OUT).
ra8_usb_addr_field_t
USBADDR field masks.
@ k_ra8_usbaddr_addr_mask
7-bit USB address [6:0].
ra8_usb_fifosel_field_t
CFIFOSEL / DxFIFOSEL field masks.
@ k_ra8_fifosel_rcnt
Read count mode.
@ k_ra8_fifosel_mbw_msk
MBW field mask.
@ k_ra8_fifosel_bigend
Big-endian access.
@ k_ra8_fifosel_dreqe
DREQ enable (DMA).
@ k_ra8_fifosel_mbw_32
32-bit FIFO access width.
@ k_ra8_fifosel_mbw_8
8-bit FIFO access width.
@ k_ra8_fifosel_isel
CFIFO direction (DCP only).
@ k_ra8_fifosel_mbw_16
16-bit FIFO access width.
@ k_ra8_fifosel_rew
Buffer rewind.
@ k_ra8_fifosel_curpipe
Current pipe select [3:0].
@ k_ra8_fifosel_dclrm
Auto FIFO clear mode.
ra8_usb_size_t
Total byte size of the modelled USB register window.
@ k_ra8_usb_window_bytes
0x070 + (9 * 2) = 0x082 bytes.
ra8_usb_ctsq_t
Control-transfer-stage values reported in INTSTS0.CTSQ[2:0].
@ k_ra8_ctsq_sqer
Sequence error.
@ k_ra8_ctsq_rdss
Control read status stage.
@ k_ra8_ctsq_rdds
Control read data stage.
@ k_ra8_ctsq_wrss
Control write status stage.
@ k_ra8_ctsq_idle
Idle / setup stage end.
@ k_ra8_ctsq_wrds
Control write data stage.
@ k_ra8_ctsq_wrnd
Control write nodata status.
static volatile r_usb_regs_t * ra8_usb_hs(void)
Get pointer to the USB HS controller register block.
ra8_usb_pipecfg_field_t
PIPECFG field masks / shifts used by the driver.
@ k_ra8_pipecfg_epnum_mask
Endpoint number [3:0].
@ k_ra8_pipecfg_dir_in
1 = IN, 0 = OUT (peri).
@ k_ra8_pipecfg_type_intr
Type = interrupt.
@ k_ra8_pipecfg_dblb
Double-buffer mode.
@ k_ra8_pipecfg_shtnak
Auto NAK on short pkt.
@ k_ra8_pipecfg_type_bulk
Type = bulk.
@ k_ra8_pipecfg_type_iso
Type = isochronous.
@ k_ra8_pipecfg_type_mask
Type field mask.
@ k_ra8_pipecfg_bfre
BRDY notify on read end.
ra8_usb_intsts0_mask_t
INTSTS0 multi-bit field masks.
@ k_ra8_intsts0_mask_dvsq
Device state.
@ k_ra8_intsts0_mask_valid
SETUP packet detect flag.
@ k_ra8_intsts0_mask_vbsts
VBUS input port level.
@ k_ra8_intsts0_mask_ctsq
Control transfer stage.
ra8_usb_intenb0_bit_t
INTENB0 / INTSTS0 bit positions (the layouts match).
@ k_ra8_int0_bit_bemp
Buffer-empty interrupt.
@ k_ra8_int0_bit_dvst
Device-state transition.
@ k_ra8_int0_bit_brdy
Buffer-ready interrupt.
@ k_ra8_int0_bit_ctrt
Control-transfer-stage transition.
@ k_ra8_int0_bit_sofr
Start-of-Frame.
@ k_ra8_int0_bit_vbse
VBUS change.
@ k_ra8_int0_bit_nrdy
Buffer-not-ready interrupt.
@ k_ra8_int0_bit_rsme
Resume.
ra8_usb_addr_t
Per-instance base addresses for the two USB controllers.
@ k_ra8_usb_hs0_base_addr
USB High-Speed base.
@ k_ra8_usb_fs0_base_addr
USB Full-Speed base.
ra8_usb_dvsq_t
Device-state values reported in INTSTS0.DVSQ[2:0].
@ k_ra8_dvsq_suspend
Suspended (any sub-state).
@ k_ra8_dvsq_address
Address assigned.
@ k_ra8_dvsq_default
Default (post bus reset).
@ k_ra8_dvsq_configured
Configured.
@ k_ra8_dvsq_powered
Powered (no reset yet).
ra8_usb_limits_t
Pipe / endpoint count constants.
@ k_ra8_usb_pad_5
Reserved length (5 hwords).
@ k_ra8_usb_dcp_max_packet_fs
EP0 max packet at FS / HS-FS.
@ k_ra8_usb_pipectr_count
PIPECTR[9] = PIPE1..PIPE9.
@ k_ra8_usb_pad_3
Reserved length (3 hwords).
@ k_ra8_usb_pad_8
Reserved length (8 hwords).
@ k_ra8_usb_pipe_count
DCP (pipe 0) + PIPE1..PIPE9.
@ k_ra8_usb_pad_2
Reserved length (2 hwords).
static volatile r_usb_regs_t * ra8_usb_fs(void)
Compile-time offset and size insurance for r_usb_regs_t.
ra8_usbhs_offset_t
Byte offsets of USBHS-only registers not modelled in r_usb_regs_t.
@ k_ra8_usbhs_off_lpsts
LPSTS : SUSPENDM gate.
@ k_ra8_usbhs_off_physet
PHYSET : embedded-PHY setup.
@ k_ra8_usbhs_off_pllsta
PLLSTA : PLL lock flag.
ra8_usbhs_buswait_t
BUSWAIT canonical value (HUM Ch 37 "BUSWAIT").
@ k_ra8_buswait_default
4-wait + b11-b8 reserved-write.
USB FS / HS register window (device-mode subset).
volatile uint16_t D1FIFOCTR
+0x02E DMA FIFO 1 control.
volatile uint16_t USBINDX
+0x058 USB Request wIndex.
volatile uint16_t NRDYENB
+0x038 NRDY Interrupt Enable.
volatile uint16_t DCPCTR
+0x060 DCP Control.
volatile uint16_t USBVAL
+0x056 USB Request wValue.
volatile uint16_t CFIFOCTR
+0x022 Control FIFO control.
volatile uint16_t CFIFOSEL
+0x020 Control FIFO select.
volatile uint16_t DCPMAXP
+0x05E DCP Max Packet.
volatile uint16_t USBADDR
+0x050 USB Address.
volatile uint16_t PIPECTR[k_ra8_usb_pipectr_count]
+0x070 PIPE1..9 ctrl.
volatile uint16_t _r6
+0x034 Reserved.
volatile uint16_t _r4
+0x01E Reserved.
volatile uint16_t CFIFO
+0x014 Control FIFO data port.
volatile uint16_t INTENB0
+0x030 Interrupt Enable 0.
volatile uint16_t INTSTS0
+0x040 Interrupt Status 0.
volatile uint16_t PIPEPERI
+0x06E Selected pipe period.
volatile uint16_t USBLENG
+0x05A USB Request wLength.
volatile uint16_t SYSCFG
+0x000 System Configuration.
volatile uint16_t SYSSTS0
+0x004 System Status 0.
volatile uint16_t DVSTCTR0
+0x008 Device State Control.
volatile uint16_t SOFCFG
+0x03C SOF Output Configuration.
volatile uint16_t BRDYENB
+0x036 BRDY Interrupt Enable.
volatile uint16_t PIPEMAXP
+0x06C Selected pipe max packet.
volatile uint16_t _r9
+0x04E Reserved.
volatile uint16_t BEMPSTS
+0x04A BEMP Interrupt Status.
volatile uint16_t _r2
+0x016 Reserved.
volatile uint16_t PIPEBUF
+0x06A Selected pipe buffer.
volatile uint16_t PIPECFG
+0x068 Selected pipe config.
volatile uint16_t INTSTS1
+0x042 Interrupt Status 1.
volatile uint16_t BUSWAIT
+0x002 CPU bus wait.
volatile uint16_t FRMNUM
+0x04C Frame Number.
volatile uint16_t D1FIFO
+0x01C DMA FIFO 1 data port.
volatile uint16_t INTENB1
+0x032 Interrupt Enable 1.
volatile uint16_t DCPCFG
+0x05C DCP Configuration.
volatile uint16_t D0FIFOSEL
+0x028 DMA FIFO 0 select.
volatile uint16_t NRDYSTS
+0x048 NRDY Interrupt Status.
volatile uint16_t D0FIFOCTR
+0x02A DMA FIFO 0 control.
volatile uint16_t BEMPENB
+0x03A BEMP Interrupt Enable.
volatile uint16_t PIPESEL
+0x064 Pipe window select.
volatile uint16_t _rc
+0x066 Reserved.
volatile uint16_t _r7
+0x03E Reserved.
volatile uint16_t _r3
+0x01A Reserved.
volatile uint16_t _r5[k_ra8_usb_pad_2]
Reserved.
volatile uint16_t _rb
+0x062 Reserved.
volatile uint16_t _r8
+0x044 Reserved.
volatile uint16_t BRDYSTS
+0x046 BRDY Interrupt Status.
volatile uint16_t D0FIFO
+0x018 DMA FIFO 0 data port.
volatile uint16_t D1FIFOSEL
+0x02C DMA FIFO 1 select.
volatile uint16_t _r1[k_ra8_usb_pad_5]
Reserved.
volatile uint16_t USBREQ
+0x054 USB Request type/bRequest.
volatile uint16_t _ra
+0x052 Reserved.
volatile uint16_t _r0
+0x006 Reserved.