ra8_usb_phy.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_time.h"
#include "ra8_usb.h"
#include "ra8_usb_internal.h"
#include "ra8_usb_regs.h"
 
static const char* s_tag = "USB";
 
/* =============================================================================
 * USBHS PHY + shared module bring-up
 * =============================================================================
 */
 
/* =============================================================================
 * Lifecycle
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_usbhs_delay_1us_iters = 2000U, 
  /* PHY analog PLL can take multiple ms to lock at cold start; FSP
   * uses an unbounded while loop. We pick 5 million NOP-spins
   * (~5 ms ceiling at 1 GHz Cortex-M85) which is well above the
   * worst-case observed lock time but still bounded for NASA Rule 2. */
  k_ra8_usbhs_pll_lock_poll_limit = 5000000U, 
  /* Per-CLKSEL bisect attempt: ~50 ms ceiling at 1 GHz so the 4-attempt
   * sweep stays under the 250 ms total wall-time budget mandated by the
   * USB-HS bring-up debug spec. */
  k_ra8_usbhs_pll_lock_attempt_limit = 50000000U / 100U, 
  k_ra8_usbhs_scke_poll_limit        = 200000U,          
  k_ra8_usbhs_probe_hi_shift         = 16U,              
  k_ra8_usbhs_probe_lo_mask          = 0x0000FFFFU,      
} ra8_usbhs_init_local_t;

typedef enum : uint8_t {
  k_ra8_usbhs_clksel_attempts_n = 4U,    
  k_ra8_usbhs_clksel_no_winner  = 0xFFU, 
} ra8_usbhs_clksel_attempt_t;

typedef enum : uint8_t {
  k_ra8_usbhs_phy_step_hse_set      = 1U, 
  k_ra8_usbhs_phy_step_clksel_12    = 2U, 
  k_ra8_usbhs_phy_step_dirpd_clear  = 3U, 
  k_ra8_usbhs_phy_step_pll_released = 4U, 
  k_ra8_usbhs_phy_step_usbe_set     = 5U, 
  k_ra8_usbhs_phy_step_suspendm_set = 6U, 
  k_ra8_usbhs_phy_step_pll_locked   = 7U, 
} ra8_usbhs_phy_step_t;

static volatile uint8_t s_phy_step_probe = 0U;

static volatile uint32_t s_usbhs_init_probe = 0U;

static volatile uint16_t s_usbhs_pllsta_probe = 0U;

static volatile uint8_t s_clksel_winner = (uint8_t)k_ra8_usbhs_clksel_no_winner;

static volatile uint16_t s_clksel_attempt_pllsta[4] = {0U, 0U, 0U, 0U};

RA8_INTERNAL
static void internal_usb_delay_1us(void)
{
  for (volatile uint32_t i = 0U; i < (uint32_t)k_ra8_usbhs_delay_1us_iters; ++i) {
    __asm__ volatile("nop");
  }
}

RA8_INTERNAL
static void internal_usbhs_enable_syscfg(volatile r_usb_regs_t* reg)
{
  /* HUM Ch 37.2.1 "SYSCFG : System Configuration Control Register", p 2061 */
  reg->SYSCFG = (uint16_t)(reg->SYSCFG & (uint16_t)~(uint16_t)(1U << k_ra8_syscfg_bit_drpd));
  reg->SYSCFG = (uint16_t)(reg->SYSCFG | (uint16_t)(1U << k_ra8_syscfg_bit_usbe));
 
  const uint32_t lo  = s_usbhs_init_probe & (uint32_t)k_ra8_usbhs_probe_lo_mask;
  const uint32_t hi  = (uint32_t)reg->SYSCFG << (uint32_t)k_ra8_usbhs_probe_hi_shift;
  s_usbhs_init_probe = lo | hi;
}

RA8_INTERNAL
static ra8_err_t internal_usbhs_wait_pll_lock_short(void)
{
  volatile const uint16_t* const pllsta = ra8_usbhs_pllsta();
  ra8_err_t                      lock   = k_ra8_err_hw_timeout;
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_usbhs_pll_lock_attempt_limit; ++i) {
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
    if (ra8_fake_mmio_wait_eval(pllsta, i, ((*pllsta & (uint16_t)k_ra8_pllsta_plllock) != 0U))) {
      lock = k_ra8_ok;
      break;
    }
#else
    if ((*pllsta & (uint16_t)k_ra8_pllsta_plllock) != 0U) {
      lock = k_ra8_ok;
      break;
    }
#endif
  }
  s_usbhs_pllsta_probe = *pllsta;
  return lock;
}

RA8_INTERNAL
static void internal_usbhs_arm_phy_reset(volatile uint16_t* physet_reg, uint16_t clksel_value)
{
  /* HUM Ch 37.2.17 PHYSET, p 2080: assert PHY power-down and PLL
   * reset, mask out CLKSEL[1:0], then OR in the candidate field. */
  uint16_t v  = *physet_reg;
  v           = (uint16_t)(v | (uint16_t)k_ra8_physet_dirpd | (uint16_t)k_ra8_physet_pllreset);
  v           = (uint16_t)(v & (uint16_t)~(uint16_t)k_ra8_physet_clksel);
  v           = (uint16_t)(v | (uint16_t)(clksel_value & (uint16_t)k_ra8_physet_clksel));
  *physet_reg = v;
}

RA8_INTERNAL
static ra8_err_t internal_usbhs_try_clksel(volatile uint16_t* physet,
                                           volatile uint16_t* lpsts,
                                           uint16_t           clksel_value)
{
  /* Drop SUSPENDM so the PHY clock is gated; subsequent PHYSET writes
   * are then sequenced through a single SUSPENDM 0->1 transition. */
  *lpsts = (uint16_t)(*lpsts & (uint16_t)~(uint16_t)k_ra8_lpsts_suspendm);
  internal_usb_delay_1us();
 
  internal_usbhs_arm_phy_reset(physet, clksel_value);
  internal_usb_delay_1us();
 
  /* Release DIRPD (PHY analog up), wait 1 ms, release PLLRESET. */
  *physet = (uint16_t)(*physet & (uint16_t)~(uint16_t)k_ra8_physet_dirpd);
  ra8_delay_ms(1U);
  *physet = (uint16_t)(*physet & (uint16_t)~(uint16_t)k_ra8_physet_pllreset);
 
  /* HUM Ch 37.2.43 LPSTS, p 2111: SUSPENDM=1 starts the PHY clock,
   * which both commits any previously-latched PHYSET writes and
   * begins the PLL lock countdown. */
  *lpsts = (uint16_t)(*lpsts | (uint16_t)k_ra8_lpsts_suspendm);
 
  return internal_usbhs_wait_pll_lock_short();
}

ra8_err_t priv_usbhs_phy_bringup(volatile r_usb_regs_t* reg)
{
  volatile uint16_t* const physet = ra8_usbhs_physet();
  volatile uint16_t* const lpsts  = ra8_usbhs_lpsts();
 
  /* Step 1: SYSCFG.HSE = 1 (mirrors FSP `hw_usb_set_hse`, called from
   * r_usb_basic.c BEFORE hw_usb_pmodule_init). HUM Ch 37 "SYSCFG"
   * register, p 2060. */
  reg->SYSCFG      = (uint16_t)(reg->SYSCFG | (uint16_t)(1U << k_ra8_syscfg_bit_hse));
  s_phy_step_probe = (uint8_t)k_ra8_usbhs_phy_step_hse_set;
 
  /* Step 2: CLKSEL = 24 MHz (PHYSET[5:4] = 11b, value 0x30).
   *
   * Per HUM Ch 37.3.3 "Supplying the Clock", Table 37.17 (p 2120) the
   * USB-PHY internal PLL takes its reference clock DIRECTLY FROM THE
   * EXTAL PIN -- not from USB60CLK. Allowed EXTAL frequencies are 12,
   * 20, 24 or 48 MHz; PHYSET.CLKSEL[1:0] selects which one.
   *
   * EK-RA8D2 fits a 24 MHz crystal (see ra8_cgc.c::k_ra8_pll2_local_t
   * comments), so CLKSEL must be 11b (k_ra8_physet_clksel_24). USB60CLK
   * (60 MHz, PLL2P/4) is still required -- it is the LINK domain clock
   * for the USBHS module itself -- but it does NOT feed the PHY UTMI
   * PLL. Earlier revisions of this code mis-modeled CLKSEL as
   * "USB60CLK / 5 = 12 MHz" and bisected over {12,48,24,20}; the host
   * never enumerated because the PHY PLL was locking at the wrong
   * frequency, producing malformed HS chirp K signaling. */
  s_phy_step_probe = (uint8_t)k_ra8_usbhs_phy_step_clksel_12;
  const ra8_err_t lock_err =
    internal_usbhs_try_clksel(physet, lpsts, (uint16_t)k_ra8_physet_clksel_24);
  s_clksel_attempt_pllsta[0] = s_usbhs_pllsta_probe;
  s_usbhs_init_probe         = (uint32_t)*physet;
 
  if (lock_err != k_ra8_ok) {
    s_clksel_winner = (uint8_t)k_ra8_usbhs_clksel_no_winner;
    ra8_log_error(s_tag, "usbhs: PHY PLL lock timeout (CLKSEL=24)");
  } else {
    s_clksel_winner  = (uint8_t)k_ra8_physet_clksel_24;
    s_phy_step_probe = (uint8_t)k_ra8_usbhs_phy_step_pll_locked;
 
    /* HUM Figure 37.2 p 2121: USBE/DRPD are programmed AFTER PLLLOCK
     * is observed. Internally splits into a separate helper to keep
     * each function under the NASA Rule 4 budget. */
    internal_usbhs_enable_syscfg(reg);
    s_phy_step_probe = (uint8_t)k_ra8_usbhs_phy_step_usbe_set;
 
    /* HUM Ch 37.2.2 "BUSWAIT : CPU Bus Wait Register", p 2063 */
    reg->BUSWAIT = (uint16_t)k_ra8_buswait_default;
    *physet      = (uint16_t)(*physet | (uint16_t)k_ra8_physet_repsel_16);
  }
  return lock_err;
}

void priv_usb_init_common(volatile r_usb_regs_t* reg)
{
  /* HUM Ch 36.2.7 "CFIFOSEL : CFIFO Port Select Register", p 1976 */
  /* HUM Ch 37.2.8 "CFIFOSEL : CFIFO Port Select Register", p 2071 */
  reg->CFIFOSEL  = k_ra8_fifosel_mbw_16;
  reg->D0FIFOSEL = k_ra8_fifosel_mbw_16;
  reg->D1FIFOSEL = k_ra8_fifosel_mbw_16;
 
  /* HUM Ch 36.2.20 "DCPMAXP : DCP Max Packet Size Register", p 1999 */
  /* HUM Ch 37.2.30 "DCPMAXP : DCP Max Packet Size Register", p 2092 */
  reg->DCPCFG  = 0U;
  reg->DCPMAXP = k_ra8_usb_dcp_max_packet;
  reg->DCPCTR  = 0U;
 
  /* HUM Ch 37.2.18 INTSTS0 Note 3 (p 2082): "To clear the CTRT, DVST,
   * SOFR, RESM, or VBINT flags, write 0 only to the flags to be cleared.
   * Write 1 to the other flags. Do not write 0 to the status flags
   * indicating 0." A wholesale ``INTSTS0 = 0`` write therefore clears
   * any stale CTRT/DVST/SOFR/RESM/VBINT edges that the PHY bring-up
   * sequence latched (mirrors FSP IP1 ``hw_usb_pmodule_init``: see
   * r_usb_preg_access.c::hw_usb_pmodule_init which writes
   * ``INTSTS0 = 0`` immediately before INTENB0 on the HS branch).
   * Without this flush a stale RESM/VBINT bit gets ORed into every
   * polled-dispatch snapshot and clutters the JLink-readable
   * ``s_intsts0_observed_or`` probe (observed value 0xD0D0 with bits
   * 14/15 set even though the host issued no real resume). */
  reg->INTSTS0 = 0U;
 
  /* HUM Ch 36.2.10 "INTENB0 : Interrupt Enable Register 0", p 1980.
   * Mirrors FSP r_usb_basic.c::usb_pmodule_init mask: BEMP, BRDY, NRDY,
   * CTRT, DVST, SOFR, RSME, VBSE. Enabling SOFR + RSME is required for
   * HS so the IP latches resume / SOF events in INTSTS0; without RSME
   * a host wake from suspend leaves the device asleep. */
  /* SOFR and RSME are intentionally NOT enabled here:
   *   - SOFR fires every 125us on HS (= 8 kHz);
   *   - RSME stays asserted on USBHS via the PHY's USBR signal
   *     while the host holds the bus in resume signalling;
   * Both starve PendSV and the demo worker thread never gets
   * scheduled. NRDY is still useful (drives the bridge's per-pipe
   * NAK re-arm) and does not cause a storm on its own. RSME / SOFR
   * status is still readable from INTSTS0 for poll-style drivers. */
  reg->INTENB0 = (uint16_t)((1U << k_ra8_int0_bit_bemp) | (1U << k_ra8_int0_bit_brdy) |
                            (1U << k_ra8_int0_bit_nrdy) | (1U << k_ra8_int0_bit_ctrt) |
                            (1U << k_ra8_int0_bit_dvst) | (1U << k_ra8_int0_bit_vbse));
  reg->INTENB1 = 0U;
  reg->BRDYENB = 0U;
  reg->NRDYENB = 0U;
  reg->BEMPENB = 0U;
}

ra8_err_t priv_usbfs_module_bringup(volatile r_usb_regs_t* reg)
{
  /* HUM Ch 36.2.1 "SYSCFG : System Configuration Control Register", p 1967 */
  reg->SYSCFG          = (uint16_t)(reg->SYSCFG | (uint16_t)(1U << k_ra8_syscfg_bit_scke));
  ra8_err_t status     = k_ra8_err_hw_timeout;
  bool      scke_ready = false;
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_usbhs_scke_poll_limit; ++i) {
    /* HUM Ch 36.2.1 "SYSCFG : System Configuration Control Register" p 1967 */
    const bool scke_set = (reg->SYSCFG & (uint16_t)(1U << k_ra8_syscfg_bit_scke)) != 0U;
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
    /* HUM Ch 36.2.1 "SYSCFG : System Configuration Control Register" p 1967 */
    const bool observed = ra8_fake_mmio_poll(&reg->SYSCFG, i, scke_set);
#else
    const bool observed = scke_set;
#endif
    if (observed) {
      scke_ready = true;
      break;
    }
  }
  if (scke_ready) {
    reg->SYSCFG = (uint16_t)(reg->SYSCFG & (uint16_t)~(uint16_t)(1U << k_ra8_syscfg_bit_drpd));
    reg->SYSCFG = (uint16_t)(reg->SYSCFG | (uint16_t)(1U << k_ra8_syscfg_bit_usbe));
    status      = k_ra8_ok;
  }
  return status;
}