USBHS embedded-PHY bring-up + shared FS/HS module bring-up. More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_time.h"
#include "ra8_usb.h"
#include "ra8_usb_internal.h"
#include "ra8_usb_regs.h"

Include dependency graph for ra8_usb_phy.c:

Enumerations
enum	ra8_usbhs_init_local_t : uint32_t { k_ra8_usbhs_delay_1us_iters = 2000U , k_ra8_usbhs_pll_lock_poll_limit = 5000000U , k_ra8_usbhs_pll_lock_attempt_limit = 50000000U / 100U , k_ra8_usbhs_scke_poll_limit = 200000U , k_ra8_usbhs_probe_hi_shift = 16U , k_ra8_usbhs_probe_lo_mask = 0x0000FFFFU }
	Local sentinels used by the USBHS PHY bring-up sequence. More...
enum	ra8_usbhs_clksel_attempt_t : uint8_t { k_ra8_usbhs_clksel_attempts_n = 4U , k_ra8_usbhs_clksel_no_winner = 0xFFU }
	Iteration order for the CLKSEL[1:0] bisect harness. More...
enum	ra8_usbhs_phy_step_t : uint8_t { k_ra8_usbhs_phy_step_hse_set = 1U , k_ra8_usbhs_phy_step_clksel_12 = 2U , k_ra8_usbhs_phy_step_dirpd_clear = 3U , k_ra8_usbhs_phy_step_pll_released = 4U , k_ra8_usbhs_phy_step_usbe_set = 5U , k_ra8_usbhs_phy_step_suspendm_set = 6U , k_ra8_usbhs_phy_step_pll_locked = 7U }
	Sentinel values for the per-step USBHS PHY bring-up probe. More...

Functions
static void	internal_usb_delay_1us (void)
	Microsecond busy-wait helper for USB PHY bring-up.
static void	internal_usbhs_enable_syscfg (volatile r_usb_regs_t *reg)
	Drive USBHS SYSCFG DRPD=0, USBE=1 after PLLRESET is released.
static ra8_err_t	internal_usbhs_wait_pll_lock_short (void)
	Bounded PHY PLL-lock poll for a single CLKSEL attempt.
static void	internal_usbhs_arm_phy_reset (volatile uint16_t *physet_reg, uint16_t clksel_value)
	Drive PHYSET into "PHY in reset" with the given CLKSEL field.
static ra8_err_t	internal_usbhs_try_clksel (volatile uint16_t physet, volatile uint16_t lpsts, uint16_t clksel_value)
	One iteration of the CLKSEL bisect: try a single codepoint.
ra8_err_t	priv_usbhs_phy_bringup (volatile r_usb_regs_t *reg)
	USBHS embedded-PHY bring-up (HUM Figure 37.2 p 2121).
void	priv_usb_init_common (volatile r_usb_regs_t *reg)
	Programme the post-SYSCFG common registers (FIFO, DCP, INTENB).
ra8_err_t	priv_usbfs_module_bringup (volatile r_usb_regs_t *reg)
	USBFS module bring-up (FSP hw_usb_pmodule_init IP0 branch).

Variables
static const char *	s_tag = "USB"
static volatile uint8_t	s_phy_step_probe = 0U
	Diagnostic step counter for the USBHS PHY bring-up sequence.
static volatile uint32_t	s_usbhs_init_probe = 0U
	Diagnostic capture of staged USBHS bring-up register values.
static volatile uint16_t	s_usbhs_pllsta_probe = 0U
	Diagnostic capture of PLLSTA at end of PHY bring-up.
static volatile uint8_t	s_clksel_winner = (uint8_t)k_ra8_usbhs_clksel_no_winner
	Diagnostic capture of the PHYSET.CLKSEL[1:0] codepoint that produced PLL lock during the bisect harness.
static volatile uint16_t	s_clksel_attempt_pllsta [4] = {0U, 0U, 0U, 0U}
	Per-attempt PLLSTA capture array for the bisect harness.

Detailed Description

USBHS embedded-PHY bring-up + shared FS/HS module bring-up.

Tag: [Ring 3 / HAL] {World: NS}

USBHS (IP1) embedded-UTMI-PHY bring-up sequence (HUM Ch 37.3.3, Figure 37.2 p 2121) plus the shared post-SYSCFG common-register programming and the USBFS (IP0) module bring-up. Split out of ra8_usb.c so every translation unit stays under the 1000-line cap; the three externally-called entry points (priv_usbhs_phy_bringup / priv_usb_init_common / priv_usbfs_module_bringup) are declared in ra8_usb_internal.h. Modelled on FSP r_usb_preg_access.c; no FSP source ships in this tree.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file ra8_usb_phy.c.

Enumeration Type Documentation

◆ ra8_usbhs_clksel_attempt_t

enum ra8_usbhs_clksel_attempt_t : uint8_t

Iteration order for the CLKSEL[1:0] bisect harness.

HUM Ch 37.2.17 PHYSET CLKSEL[1:0] bit-field, p 2080:

00b = 12 MHz (canonical UTMI reference; PHY divides USB60CLK by 5 internally to obtain 12 MHz from a 60 MHz USB60CLK)
01b = 48 MHz
10b = 20 MHz
11b = 24 MHz (PHYSET reset value)

USB60CKDIVCR is now /4 so USB60CLK = PLL2P/4 = 240/4 = 60.000 MHz, matching the HUM Ch 37.3.3 named-rate requirement (p 2102: "A 60-MHz clock must be supplied"). With a 60 MHz USB60CLK the canonical CLKSEL is 12 MHz (the standard UTMI+ reference), so the bisect tries CLKSEL=12 first and only falls through to 48 / 20 / 24 as a defensive sweep if a CGC regression delivers an unexpected USB60CLK rate. Capture the winner (or 0xFF on full sweep failure) into s_clksel_winner.

Enumerator
k_ra8_usbhs_clksel_attempts_n	RA8 usbhs clksel attempts n.
k_ra8_usbhs_clksel_no_winner	Sentinel: bisect exhausted.

Definition at line 97 of file ra8_usb_phy.c.

◆ ra8_usbhs_init_local_t

enum ra8_usbhs_init_local_t : uint32_t

Local sentinels used by the USBHS PHY bring-up sequence.

delay_1us_iters – NOP-loop iteration count for ~1 us at 1 GHz.
pll_lock_poll_limit – bounded spin count for PLLSTA.PLLLOCK wait (~200k iters; covers worst-case PHY analog ramp).
scke_poll_limit – same bound for the FS-path SCKE settle wait.
probe_hi_shift – shift to pack SYSCFG into the high half of s_usbhs_init_probe.
probe_lo_mask – mask of the low half of the probe word.

Enumerator
k_ra8_usbhs_delay_1us_iters	RA8 usbhs delay 1us iters.
k_ra8_usbhs_pll_lock_poll_limit	RA8 usbhs pll lock poll limit.
k_ra8_usbhs_pll_lock_attempt_limit	RA8 usbhs pll lock attempt limit.
k_ra8_usbhs_scke_poll_limit	RA8 usbhs scke poll limit.
k_ra8_usbhs_probe_hi_shift	RA8 usbhs probe hi shift.
k_ra8_usbhs_probe_lo_mask	RA8 usbhs probe lo mask.

Definition at line 61 of file ra8_usb_phy.c.

◆ ra8_usbhs_phy_step_t

enum ra8_usbhs_phy_step_t : uint8_t

Sentinel values for the per-step USBHS PHY bring-up probe.

Each value marks a completed sub-step of priv_usbhs_phy_bringup. A JLink read of s_phy_step_probe pinpoints the furthest-reached step on a stalled boot.

Enumerator
k_ra8_usbhs_phy_step_hse_set	SYSCFG.HSE asserted.
k_ra8_usbhs_phy_step_clksel_12	PHYSET CLKSEL forced to 12.
k_ra8_usbhs_phy_step_dirpd_clear	PHY analog powered.
k_ra8_usbhs_phy_step_pll_released	PHY PLLRESET cleared.
k_ra8_usbhs_phy_step_usbe_set	SYSCFG DRPD=0 USBE=1.
k_ra8_usbhs_phy_step_suspendm_set	LPSTS SUSPENDM=1.
k_ra8_usbhs_phy_step_pll_locked	PLLSTA.PLLLOCK observed.

Definition at line 110 of file ra8_usb_phy.c.

Function Documentation

◆ internal_usb_delay_1us()

void internal_usb_delay_1us ( void )

static

Microsecond busy-wait helper for USB PHY bring-up.

Cortex-M85 at 1 GHz: ~1000 cycles per microsecond. We use a NOP loop calibrated to comfortably exceed 1 us so PHY power-up settling completes. FSP r_usb_preg_access.c calls usb_cpu_delay_1us – this is the local equivalent.

Precondition: Caller is in init context (busy-wait blocks the CPU).; CPU clock is the one assumed by k_ra8_usbhs_delay_1us_iters.

Postcondition: No state mutation; loop iteration count is bounded.; At least 1 us has elapsed.

Note: Not thread-safe; calibrated for 1 GHz Cortex-M85.

Since: 0.1.0

Definition at line 214 of file ra8_usb_phy.c.

References k_ra8_usbhs_delay_1us_iters.

Referenced by internal_usbhs_try_clksel().

◆ internal_usbhs_arm_phy_reset()

void internal_usbhs_arm_phy_reset	(	volatile uint16_t *	physet_reg,
		uint16_t	clksel_value )

static

Drive PHYSET into "PHY in reset" with the given CLKSEL field.

Asserts DIRPD=1 and PLLRESET=1, then writes the chosen CLKSEL[1:0] codepoint. HUM Ch 37.2.17 PHYSET, p 2080 Table: 00b=12 MHz, 01b=48 MHz, 10b=20 MHz, 11b=24 MHz. Used by both the canonical bring-up path and the CLKSEL bisect harness.

Parameters

[in]	physet_reg	PHYSET register pointer (ra8_usbhs_physet()).
[in]	clksel_value	Pre-shifted CLKSEL field value (0x00, 0x10, 0x20, or 0x30).

Precondition: physet_reg non-null.; LPSTS.SUSPENDM may be 0 or 1; HUM Ch 37.2.43 LPSTS, p 2111 states only a small whitelist of registers can be written while SUSPENDM=0 and PHYSET is not on it. The harness clears SUSPENDM-then-sets it again per attempt to flush latched writes regardless.

Postcondition: PHYSET: DIRPD=1, PLLRESET=1, CLKSEL field = clksel_value.; No other PHYSET fields (REPSEL, HSEB, CDPEN) are touched.

Note: Not thread-safe; init context only.

Since: 0.1.0

Definition at line 321 of file ra8_usb_phy.c.

References k_ra8_physet_clksel, k_ra8_physet_dirpd, and k_ra8_physet_pllreset.

Referenced by internal_usbhs_try_clksel().

◆ internal_usbhs_enable_syscfg()

void internal_usbhs_enable_syscfg ( volatile r_usb_regs_t * reg )

static

Drive USBHS SYSCFG DRPD=0, USBE=1 after PLLRESET is released.

Splits the SYSCFG mutation off from priv_usbhs_phy_bringup so each helper stays under the NASA Rule 4 / clang-tidy size budget. HSE is set separately at the start of the bring-up (mirrors FSP hw_usb_set_hse which is called BEFORE hw_usb_pmodule_init – r_usb_basic.c). Captures the SYSCFG-after-USBE value into the probe word's high half.

Parameters

[in] reg HS register block pointer.

Precondition: PHYSET DIRPD/PLLRESET are released.; SYSCFG.HSE is already 1.; s_usbhs_init_probe low half holds PHYSET-after-power-up.

Postcondition: SYSCFG: DRPD=0, USBE=1, HSE=1.; s_usbhs_init_probe high half = SYSCFG.

Note: Not thread-safe; init context only.

Since: 0.1.0

Definition at line 243 of file ra8_usb_phy.c.

References k_ra8_syscfg_bit_drpd, k_ra8_syscfg_bit_usbe, k_ra8_usbhs_probe_hi_shift, k_ra8_usbhs_probe_lo_mask, s_usbhs_init_probe, and r_usb_regs_t::SYSCFG.

Referenced by priv_usbhs_phy_bringup().

◆ internal_usbhs_try_clksel()

ra8_err_t internal_usbhs_try_clksel	(	volatile uint16_t *	physet,
		volatile uint16_t *	lpsts,
		uint16_t	clksel_value )

static

One iteration of the CLKSEL bisect: try a single codepoint.

For the given CLKSEL value:

Toggle LPSTS.SUSPENDM 1->0->1 to flush latched PHYSET writes (HUM Ch 37.2.43 LPSTS p 2111: writes to USBHS regs only take effect once the PHY clock oscillates, which happens when SUSPENDM is set to 1).
Arm PHYSET in reset with this CLKSEL.
Release DIRPD (1 us settle), wait 1 ms, release PLLRESET.
Set LPSTS.SUSPENDM = 1.
Poll PLLSTA.PLLLOCK with the per-attempt budget.

Parameters

[in]	physet	PHYSET register pointer.
[in]	lpsts	LPSTS register pointer.
[in]	clksel_value	PHYSET CLKSEL field value (0x00/10/20/30).

Returns: ra8_err_t

Return values

k_ra8_ok	PLL locked under this CLKSEL.
k_ra8_err_hw_timeout	PLL did not lock within the per-attempt window.

Precondition: SYSCFG.HSE = 1.; physet and lpsts pointers are non-null and point at the HS USBHS register block.

Postcondition: On success: PHY powered, PLLRESET cleared, SUSPENDM=1.; On failure: SUSPENDM=1 is left asserted; caller may retry the next CLKSEL value or surface the timeout.

Note: Not thread-safe; init context only.

Since: 0.1.0

Definition at line 365 of file ra8_usb_phy.c.

References internal_usb_delay_1us(), internal_usbhs_arm_phy_reset(), internal_usbhs_wait_pll_lock_short(), k_ra8_lpsts_suspendm, k_ra8_physet_dirpd, k_ra8_physet_pllreset, and ra8_delay_ms().

Referenced by priv_usbhs_phy_bringup().

◆ internal_usbhs_wait_pll_lock_short()

ra8_err_t internal_usbhs_wait_pll_lock_short ( void )

static

Bounded PHY PLL-lock poll for a single CLKSEL attempt.

Polls PLLSTA.PLLLOCK up to a ~50 ms ceiling. Captures the final PLLSTA value into s_usbhs_pllsta_probe regardless of outcome so JLink reads can see the chip's view of the PLL state.

Returns: ra8_err_t

Return values

k_ra8_ok	PLLLOCK observed within the per-attempt window.
k_ra8_err_hw_timeout	PLLLOCK never asserted.

Precondition: LPSTS.SUSPENDM = 1 and PHYSET is configured for the chosen CLKSEL value.; USB60CLK is running (PLL2P / 4 = 60 MHz).

Postcondition: Loop iteration count is bounded.; s_usbhs_pllsta_probe holds the final PLLSTA word.

Note: Not thread-safe; init context only.

Since: 0.1.0

Definition at line 275 of file ra8_usb_phy.c.

References k_ra8_err_hw_timeout, k_ra8_ok, k_ra8_pllsta_plllock, k_ra8_usbhs_pll_lock_attempt_limit, ra8_usbhs_pllsta(), and s_usbhs_pllsta_probe.

Referenced by internal_usbhs_try_clksel().

◆ priv_usb_init_common()

void priv_usb_init_common ( volatile r_usb_regs_t * reg )

Programme the post-SYSCFG common registers (FIFO, DCP, INTENB).

Shared tail of FS and HS device-mode bring-up: CFIFOSEL, DCP defaults, and the device-mode INTENB0 interrupt mask.

Parameters

[in] reg Selected USB instance register block.

Precondition: Caller has already enabled SYSCFG.USBE.; reg is non-null.

Postcondition: All listed registers carry deterministic device-mode defaults.; INTENB1 / BRDYENB / NRDYENB / BEMPENB are cleared.

Note: Not thread-safe; init context only.

Since: 0.1.0

Definition at line 495 of file ra8_usb_phy.c.

References r_usb_regs_t::BEMPENB, r_usb_regs_t::BRDYENB, r_usb_regs_t::CFIFOSEL, r_usb_regs_t::D0FIFOSEL, r_usb_regs_t::D1FIFOSEL, r_usb_regs_t::DCPCFG, r_usb_regs_t::DCPCTR, r_usb_regs_t::DCPMAXP, r_usb_regs_t::INTENB0, r_usb_regs_t::INTENB1, r_usb_regs_t::INTSTS0, k_ra8_fifosel_mbw_16, k_ra8_int0_bit_bemp, k_ra8_int0_bit_brdy, k_ra8_int0_bit_ctrt, k_ra8_int0_bit_dvst, k_ra8_int0_bit_nrdy, k_ra8_int0_bit_vbse, k_ra8_usb_dcp_max_packet, and r_usb_regs_t::NRDYENB.

Referenced by ra8_usb_device_init().

◆ priv_usbfs_module_bringup()

ra8_err_t priv_usbfs_module_bringup ( volatile r_usb_regs_t * reg )

USBFS module bring-up (FSP hw_usb_pmodule_init IP0 branch).

Sets SCKE, polls SCKE-readback, clears DRPD, sets USBE. The FS instance has no PHY-side registers (PHYSET / LPSTS / PLLSTA are HS-only) so this is a pure SYSCFG-driven sequence.

Parameters

[in] reg FS register block pointer (must be ra8_usb_fs()).

Returns: ra8_err_t

Return values

k_ra8_ok USBE asserted.

Precondition: MSTPB11 ungated; USB48CLK fed from PLL2P/5 = 48 MHz.; Caller is single-threaded init context.

Postcondition: SYSCFG: SCKE=1, DRPD=0, USBE=1.; Loop iteration count is bounded.

Note: Not thread-safe; init context only.

Since: 0.1.0

Definition at line 566 of file ra8_usb_phy.c.

References k_ra8_err_hw_timeout, k_ra8_ok, k_ra8_syscfg_bit_drpd, k_ra8_syscfg_bit_scke, k_ra8_syscfg_bit_usbe, k_ra8_usbhs_scke_poll_limit, and r_usb_regs_t::SYSCFG.

Referenced by ra8_usb_device_init().

◆ priv_usbhs_phy_bringup()

ra8_err_t priv_usbhs_phy_bringup ( volatile r_usb_regs_t * reg )

USBHS embedded-PHY bring-up (HUM Figure 37.2 p 2121).

Implements the device-mode PHY bring-up flow exactly as documented in HUM Ch 37.3.3 + Figure 37.2. The PHY UTMI internal PLL takes EXTAL directly (24 MHz on EK-RA8D2); USB60CLK = 60 MHz is the separate LINK domain clock supplied by ra8_cgc_usbhs_pll_enable.

SYSCFG |= HSE (high-speed enable, before PHY)
PHYSET |= DIRPD | PLLRESET; CLKSEL = 11b (24 MHz)
delay 1 us (HUM "Wait 1 us" after CLKSEL)
PHYSET &= ~DIRPD (release PHY analog power-down)
delay 1 ms (HUM "Wait 1 ms" after DIRPD)
PHYSET &= ~PLLRESET (release UTMI PHY PLL reset)
LPSTS |= SUSPENDM (start the PHY clock)
wait PLLSTA.PLLLOCK = 1 (UTMI PLL lock confirmation)
SYSCFG &= ~DRPD; |= USBE (enable module operation)

BUSWAIT = 0x0F04 (4-wait + reserved b11-b8)

PHYSET |= REPSEL_16 (terminator adjust cycle)

The HS instance has no SCKE bit (HUM Ch 37.2.1 "SYSCFG" register layout, p 2060); writing bit 10 there is a no-op.

Parameters

[in] reg HS register block pointer (must be ra8_usb_hs()).

Returns: ra8_err_t

Return values

k_ra8_ok	HS PHY locked and ready for DPRPU attach.
k_ra8_err_hw_timeout	PLLSTA.PLLLOCK never asserted.

Precondition: MSTPB12 ungated; USB60CLK = PLL2P / 4 = 60 MHz.; Caller is single-threaded init context.

Postcondition: On success: PHY powered, PLL locked, USBE=1, SUSPENDM=1.; BUSWAIT programmed.

Note: Not thread-safe; init context only.

Since: 0.1.0

Definition at line 427 of file ra8_usb_phy.c.

References r_usb_regs_t::BUSWAIT, internal_usbhs_enable_syscfg(), internal_usbhs_try_clksel(), k_ra8_buswait_default, k_ra8_ok, k_ra8_physet_clksel_24, k_ra8_physet_repsel_16, k_ra8_syscfg_bit_hse, k_ra8_usbhs_clksel_no_winner, k_ra8_usbhs_phy_step_clksel_12, k_ra8_usbhs_phy_step_hse_set, k_ra8_usbhs_phy_step_pll_locked, k_ra8_usbhs_phy_step_usbe_set, ra8_log_error, ra8_usbhs_lpsts(), ra8_usbhs_physet(), s_clksel_attempt_pllsta, s_clksel_winner, s_phy_step_probe, s_tag, s_usbhs_init_probe, s_usbhs_pllsta_probe, and r_usb_regs_t::SYSCFG.

Referenced by internal_host_hs_bringup(), and ra8_usb_device_init().

Variable Documentation

◆ s_clksel_attempt_pllsta

volatile uint16_t s_clksel_attempt_pllsta[4] = {0U, 0U, 0U, 0U}

static

Per-attempt PLLSTA capture array for the bisect harness.

Index = attempt number (0..3). Each slot captures the PLLSTA value observed at the end of that attempt's polling window so a JLink read of all four words tells the operator which CLKSEL codepoints saw any partial lock activity.

Note: Read-only from outside.

Warning: Direct modification breaks the diagnostic invariant.

Since: 0.1.0

Definition at line 196 of file ra8_usb_phy.c.

Referenced by priv_usbhs_phy_bringup().

◆ s_clksel_winner

volatile uint8_t s_clksel_winner = (uint8_t)k_ra8_usbhs_clksel_no_winner

static

Diagnostic capture of the PHYSET.CLKSEL[1:0] codepoint that produced PLL lock during the bisect harness.

Layout: low nibble is the masked PHYSET CLKSEL field (0x00, 0x10, 0x20, or 0x30 corresponding to 12 / 48 / 20 / 24 MHz per HUM Ch 37.2.17 PHYSET p 2080 Table). Sentinel 0xFF means the full 4-codepoint sweep completed without observing PLLSTA.PLLLOCK.

Note: Read-only from outside; written only by priv_usbhs_phy_bringup.

Warning: Direct modification breaks the diagnostic invariant.

Since: 0.1.0

Definition at line 181 of file ra8_usb_phy.c.

Referenced by priv_usbhs_phy_bringup().

◆ s_phy_step_probe

volatile uint8_t s_phy_step_probe = 0U

static

Diagnostic step counter for the USBHS PHY bring-up sequence.

Each step in priv_usbhs_phy_bringup writes a fixed sentinel here so a JLink read pinpoints the last completed step:

1 = SYSCFG.HSE asserted (pre-PHY).
2 = PHYSET DIRPD|CLKSEL set, CLKSEL field forced to 12 MHz.
3 = PHYSET DIRPD released (PHY analog powered).
4 = PHYSET PLLRESET released.
5 = SYSCFG DRPD cleared, USBE set.
6 = LPSTS.SUSPENDM set.
7 = PLLSTA.PLLLOCK observed (PHY ready).

Note: Read-only from outside; written only by the PHY bring-up.

Warning: Direct modification breaks the diagnostic invariant.

Since: 0.1.0

Definition at line 138 of file ra8_usb_phy.c.

Referenced by priv_usbhs_phy_bringup().

◆ s_tag

const char* s_tag = "USB"

static

Definition at line 36 of file ra8_usb_phy.c.

◆ s_usbhs_init_probe

volatile uint32_t s_usbhs_init_probe = 0U

static

Diagnostic capture of staged USBHS bring-up register values.

Each phase of the HS PHY bring-up writes a distinct slot here so a JLink read of this SRAM word reveals exactly which step was reached. Layout (low half = PHYSET-after-power-up, high half = SYSCFG-after-USBE-write). On a healthy boot the low half ends at DIRPD=0, PLLRESET=0, CLKSEL=0 and the high half ends at USBE|HSE = 0x081.

Note: Read-only from outside; written only by ra8_usb_device_init.

Warning: Direct modification breaks the diagnostic invariant.

Since: 0.1.0

Definition at line 155 of file ra8_usb_phy.c.

Referenced by internal_usbhs_enable_syscfg(), and priv_usbhs_phy_bringup().

◆ s_usbhs_pllsta_probe

volatile uint16_t s_usbhs_pllsta_probe = 0U

static

Diagnostic capture of PLLSTA at end of PHY bring-up.

Note: Read-only from outside; written only by ra8_usb_device_init.

Warning: Direct modification breaks the diagnostic invariant.

Since: 0.1.0

Definition at line 165 of file ra8_usb_phy.c.

Referenced by internal_usbhs_wait_pll_lock_short(), and priv_usbhs_phy_bringup().

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ ra8_usbhs_clksel_attempt_t

◆ ra8_usbhs_init_local_t

◆ ra8_usbhs_phy_step_t

Function Documentation

◆ internal_usb_delay_1us()

◆ internal_usbhs_arm_phy_reset()

◆ internal_usbhs_enable_syscfg()

◆ internal_usbhs_try_clksel()

◆ internal_usbhs_wait_pll_lock_short()

◆ priv_usb_init_common()

◆ priv_usbfs_module_bringup()

◆ priv_usbhs_phy_bringup()

Variable Documentation

◆ s_clksel_attempt_pllsta

◆ s_clksel_winner

◆ s_phy_step_probe

◆ s_tag

◆ s_usbhs_init_probe

◆ s_usbhs_pllsta_probe