main.c

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#include <stddef.h>
#include <stdint.h>
 
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cache.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_log.h"

typedef enum : uint32_t {
  k_cache_hal_baud      = 115200U, 
  k_cache_hal_buf_bytes = 4096U,   
  k_cache_hal_buf_min   = 4096U,   
} cache_hal_config_t;

typedef enum : uint8_t {
  k_cache_hal_pat_mul = 31U, 
  k_cache_hal_pat_add = 7U,  
} cache_hal_pattern_t;
 
static_assert((uint32_t)k_cache_hal_buf_bytes >= (uint32_t)k_cache_hal_buf_min,
              "cacheable self-test buffer must be at least 4 KiB");

alignas(32) static uint8_t s_cache_hal_buf[k_cache_hal_buf_bytes];

static const uint8_t k_cache_hal_pass_banner[] = "cache_hal_enable_demo: L1-cache-via-HAL PASS\r\n";

static const uint8_t k_cache_hal_fail_setup[] = "cache_hal_enable_demo: setup FAIL\r\n";

static const uint8_t k_cache_hal_fail_rw[] = "cache_hal_enable_demo: cacheable-RW FAIL\r\n";

[[noreturn]] static void cache_hal_wfi_forever(void)
{
  while (1) {
    __asm volatile("wfi");
  }
}

static bool cache_hal_test_cacheable_rw(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_cache_hal_buf_bytes; i++) {
    s_cache_hal_buf[i] =
      (uint8_t)((i * (uint32_t)k_cache_hal_pat_mul) + (uint32_t)k_cache_hal_pat_add);
  }
 
  /* Force the freshly written (dirty) lines back to SRAM and drop them, so the
   * verify pass below must refill from memory -- the full write-back + refill
   * round-trip with the HAL-enabled D-cache on. */
  if (ra8_cache_dcache_clean_invalidate_by_addr(s_cache_hal_buf,
                                                (uint32_t)sizeof(s_cache_hal_buf)) != k_ra8_ok) {
    return false;
  }
 
  for (uint32_t i = 0U; i < (uint32_t)k_cache_hal_buf_bytes; i++) {
    const uint8_t expected =
      (uint8_t)((i * (uint32_t)k_cache_hal_pat_mul) + (uint32_t)k_cache_hal_pat_add);
    if (s_cache_hal_buf[i] != expected) {
      return false;
    }
  }
  return true;
}

static bool cache_hal_setup(void)
{
  if (ra8_cgc_init() != k_ra8_ok) {
    return false;
  }
  if (ra8_board_uart_console_init((uint32_t)k_cache_hal_baud) != k_ra8_ok) {
    return false;
  }
  return true;
}

static void cache_hal_emit(const uint8_t* line, size_t len)
{
  if (line == nullptr) {
    return;
  }
  if (len == 0U) {
    return;
  }
  (void)ra8_board_uart_console_write(line, len);
  (void)ra8_board_uart_console_flush();
}

void main(void)
{
  ra8_log_init();
  ra8_log_info("CACHE_HAL", "==== cache_hal_enable_demo: L1 cache via ra8_cache HAL ====");
 
  if (!cache_hal_setup()) {
    ra8_log_info("CACHE_HAL", "setup FAILED (CGC / console) -- halting");
    cache_hal_emit(k_cache_hal_fail_setup, sizeof(k_cache_hal_fail_setup) - 1U);
    cache_hal_wfi_forever();
  }
 
  if (!cache_hal_test_cacheable_rw()) {
    ra8_log_info("CACHE_HAL", "cacheable-RW step FAILED");
    cache_hal_emit(k_cache_hal_fail_rw, sizeof(k_cache_hal_fail_rw) - 1U);
    cache_hal_wfi_forever();
  }
 
  ra8_log_info("CACHE_HAL", "L1-cache-via-HAL PASS (cacheable RW round-trip)");
  cache_hal_emit(k_cache_hal_pass_banner, sizeof(k_cache_hal_pass_banner) - 1U);
  cache_hal_wfi_forever();
}