main.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_device.h"
#include "ra8_err.h"
#include "ra8_ethosu_kernel.h"
#include "ra8_isr.h"
#include "ra8_npu.h"
#include "ra8_npu_fake_cmd.h"
#include "ra8_npu_quant.h"
#include "ra8_npu_regs.h"
 
/*
 * Compile-time proof that the RA8P1 toolchain selection reached this TU: the NPU
 * driver + TFLite-micro Ethos-U kernel only exist when RA8_HAS_NPU is defined
 * (RA8_DEVICE_RA8P1). Building this app with the RA8D2 toolchain fails loudly here.
 */
#ifndef RA8_HAS_NPU
#error "npu_infer must be built with cmake/toolchain-ra8p1.cmake (RA8_DEVICE_RA8P1)."
#endif

typedef enum : uint32_t {
  k_npu_infer_baud        = 115200U,                 
  k_npu_infer_arena_bytes = 32U,                     
  k_npu_infer_cmd_words   = k_ra8_npu_fake_word_num, 
  k_npu_infer_hex_digits  = 8U,                      
  k_npu_infer_hex_shift   = 4U,                      
  k_npu_infer_hex_mask    = 0x0FU,                   
} npu_infer_size_t;

typedef enum : uint8_t {
  k_npu_infer_region_weights = 0U, 
  k_npu_infer_region_input   = 1U, 
  k_npu_infer_region_output  = 2U, 
  k_npu_infer_region_count   = 3U, 
} npu_infer_region_t;

typedef enum : int32_t {
  k_npu_infer_zero_point = 4,    
  k_npu_infer_addk       = 0x10, 
  k_npu_infer_seed_mask  = 15,   
  k_npu_infer_byte_mask  = 0xFF, 
} npu_infer_quant_t;

typedef enum : uint32_t {
  k_npu_infer_fnv_offset = 0x811C9DC5U, 
  k_npu_infer_fnv_prime  = 0x01000193U, 
} npu_infer_fnv_t;

static const float s_infer_scale = 0.5F;

static const float s_infer_deq_tol = 0.001F;

static uint32_t s_npu_cmd_stream[k_npu_infer_cmd_words];

static uint8_t s_npu_weights[k_npu_infer_arena_bytes];

static float s_infer_input_f[k_npu_infer_arena_bytes];

static uint8_t s_npu_input[k_npu_infer_arena_bytes];

static uint8_t s_npu_output[k_npu_infer_arena_bytes];

static float s_infer_output_f[k_npu_infer_arena_bytes];

volatile uint32_t g_npu_infer_pass = 0U;

RA8_INTERNAL static void internal_npu_infer_panic_halt(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

RA8_INTERNAL static void internal_npu_infer_park(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

RA8_INTERNAL static void internal_npu_infer_setup_or_halt(void)
{
  if (ra8_cgc_init() != k_ra8_ok) {
    internal_npu_infer_panic_halt();
  }
  if (ra8_board_uart_console_init((uint32_t)k_npu_infer_baud) != k_ra8_ok) {
    internal_npu_infer_panic_halt();
  }
  if (ra8_isr_init() != k_ra8_ok) {
    internal_npu_infer_panic_halt();
  }
}

RA8_INTERNAL static void internal_npu_infer_build_stream(void)
{
  s_npu_cmd_stream[k_ra8_npu_fake_word_op] =
    (uint32_t)k_ra8_npu_fake_magic | (uint32_t)k_ra8_npu_fake_op_addk;
  s_npu_cmd_stream[k_ra8_npu_fake_word_src]   = (uint32_t)k_npu_infer_region_input;
  s_npu_cmd_stream[k_ra8_npu_fake_word_dst]   = (uint32_t)k_npu_infer_region_output;
  s_npu_cmd_stream[k_ra8_npu_fake_word_count] = (uint32_t)k_npu_infer_arena_bytes;
  s_npu_cmd_stream[k_ra8_npu_fake_word_const] = (uint32_t)k_npu_infer_addk;
}

RA8_INTERNAL static ra8_err_t internal_npu_infer_prepare_input(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_npu_infer_arena_bytes; i++) {
    s_infer_input_f[i] = s_infer_scale * (float)((int32_t)i & (int32_t)k_npu_infer_seed_mask);
    s_npu_output[i]    = 0U;
  }
  return ra8_npu_quantize_u8(s_infer_input_f,
                             s_npu_input,
                             (size_t)k_npu_infer_arena_bytes,
                             s_infer_scale,
                             (int32_t)k_npu_infer_zero_point);
}

RA8_INTERNAL static ra8_err_t internal_npu_infer_run_job_irq(void)
{
  ra8_npu_job_t job                           = {};
  job.cmd_stream                              = s_npu_cmd_stream;
  job.cmd_stream_bytes                        = (uint32_t)sizeof(s_npu_cmd_stream);
  job.region_count                            = (uint8_t)k_npu_infer_region_count;
  job.region_base[k_npu_infer_region_weights] = (uint64_t)(uintptr_t)s_npu_weights;
  job.region_base[k_npu_infer_region_input]   = (uint64_t)(uintptr_t)s_npu_input;
  job.region_base[k_npu_infer_region_output]  = (uint64_t)(uintptr_t)s_npu_output;
 
  const ra8_err_t sub = ra8_npu_submit(&job);
  if (sub != k_ra8_ok) {
    return sub;
  }
  const ra8_err_t arm = ra8_npu_irq_arm();
  if (arm != k_ra8_ok) {
    return arm;
  }
  const ra8_err_t run = ra8_npu_run();
  if (run != k_ra8_ok) {
    return run;
  }
  return ra8_npu_wait_irq();
}

RA8_INTERNAL static bool internal_npu_infer_verify(uint32_t* out_check)
{
  uint32_t check = (uint32_t)k_npu_infer_fnv_offset;
  bool     ok    = true;
  for (uint32_t i = 0U; i < (uint32_t)k_npu_infer_arena_bytes; i++) {
    const int32_t expect_q =
      ((int32_t)i & (int32_t)k_npu_infer_seed_mask) + (int32_t)k_npu_infer_zero_point;
    const int32_t expect_out =
      (expect_q + (int32_t)k_npu_infer_addk) & (int32_t)k_npu_infer_byte_mask;
    const float expect_f =
      s_infer_scale * (float)((int32_t)s_npu_output[i] - (int32_t)k_npu_infer_zero_point);
    const float diff = (s_infer_output_f[i] > expect_f) ? (s_infer_output_f[i] - expect_f)
                                                        : (expect_f - s_infer_output_f[i]);
    if ((int32_t)s_npu_input[i] != expect_q) {
      ok = false; /* quantize stage */
    }
    if ((int32_t)s_npu_output[i] != expect_out) {
      ok = false; /* NPU op stage (IRQ completion) */
    }
    if (diff > s_infer_deq_tol) {
      ok = false; /* dequantize stage */
    }
    check = (check ^ (uint32_t)s_npu_output[i]) * (uint32_t)k_npu_infer_fnv_prime;
  }
  *out_check = check;
  return ok;
}
 
RA8_INTERNAL static void internal_npu_infer_write(const uint8_t* data, size_t len)
{
  (void)ra8_board_uart_console_write(data, len);
}
 
RA8_INTERNAL static void internal_npu_infer_write_hex32(uint32_t value)
{
  static const uint8_t k_hex[]                        = "0123456789ABCDEF";
  uint8_t              digits[k_npu_infer_hex_digits] = {};
  for (uint8_t i = 0U; i < (uint8_t)k_npu_infer_hex_digits; ++i) {
    const uint8_t shift =
      (uint8_t)(((uint8_t)k_npu_infer_hex_digits - 1U - i) * (uint8_t)k_npu_infer_hex_shift);
    digits[i] = k_hex[(value >> shift) & (uint32_t)k_npu_infer_hex_mask];
  }
  internal_npu_infer_write(digits, (size_t)k_npu_infer_hex_digits);
}
 
RA8_INTERNAL static void internal_npu_infer_write_status(bool ok)
{
  const uint8_t* text = ok ? (const uint8_t*)"OK" : (const uint8_t*)"FAIL";
  const size_t   len  = ok ? 2U : 4U;
  internal_npu_infer_write(text, len);
}
 
RA8_INTERNAL static void internal_npu_infer_write_verdict(bool pass)
{
  const uint8_t* text = pass ? (const uint8_t*)"PASS" : (const uint8_t*)"FAIL";
  internal_npu_infer_write(text, 4U);
}

RA8_INTERNAL static void
internal_npu_infer_emit(uint32_t id, bool tflm_ok, bool run_ok, uint32_t check, bool pass)
{
  internal_npu_infer_write((const uint8_t*)"npu-infer: id=0x", sizeof("npu-infer: id=0x") - 1U);
  internal_npu_infer_write_hex32(id);
  internal_npu_infer_write((const uint8_t*)" tflm=", sizeof(" tflm=") - 1U);
  internal_npu_infer_write_status(tflm_ok);
  internal_npu_infer_write((const uint8_t*)" irq=", sizeof(" irq=") - 1U);
  internal_npu_infer_write_status(run_ok);
  internal_npu_infer_write((const uint8_t*)" out=0x", sizeof(" out=0x") - 1U);
  internal_npu_infer_write_hex32(check);
  internal_npu_infer_write((const uint8_t*)" verdict=", sizeof(" verdict=") - 1U);
  internal_npu_infer_write_verdict(pass);
  internal_npu_infer_write((const uint8_t*)"\r\n", sizeof("\r\n") - 1U);
  (void)ra8_board_uart_console_flush();
}

RA8_INTERNAL static bool
internal_npu_infer_execute(uint32_t* out_id, bool* out_tflm, uint32_t* out_check)
{
  *out_id    = 0U;
  *out_tflm  = (ra8_ethosu_kernel_available() == 1);
  *out_check = 0U;
 
  if (ra8_npu_init() != k_ra8_ok) {
    return false;
  }
  (void)ra8_npu_read_id(out_id);
 
  const ra8_err_t reg = ra8_isr_register((ra8_elc_event_t)k_ra8_npu_event_irq,
                                         ra8_npu_irq_handler,
                                         nullptr,
                                         (uint8_t)k_ra8_isr_prio_default,
                                         nullptr);
  if (reg != k_ra8_ok) {
    return false;
  }
  ra8_isr_globals_enable();
 
  internal_npu_infer_build_stream();
  if (internal_npu_infer_prepare_input() != k_ra8_ok) {
    return false;
  }
  if (internal_npu_infer_run_job_irq() != k_ra8_ok) {
    return false;
  }
  if (ra8_npu_dequantize_u8(s_npu_output,
                            s_infer_output_f,
                            (size_t)k_npu_infer_arena_bytes,
                            s_infer_scale,
                            (int32_t)k_npu_infer_zero_point) != k_ra8_ok) {
    return false;
  }
  return internal_npu_infer_verify(out_check);
}

void main(void)
{
  internal_npu_infer_setup_or_halt();
 
  uint32_t id    = 0U;
  bool     tflm  = false;
  uint32_t check = 0U;
  /* run_ok = init + IRQ-driven quantize/op/dequantize pipeline all matched. The
   * TFLite-micro registration (tflm) is a separate leg reported on its own field;
   * the verdict is PASS only when every leg holds. */
  const bool run_ok = internal_npu_infer_execute(&id, &tflm, &check);
  const bool pass   = run_ok && tflm && (id != 0U);
 
  g_npu_infer_pass = pass ? 1U : 0U;
  internal_npu_infer_emit(id, tflm, run_ok, check, pass);
 
  internal_npu_infer_park();
}