96typedef enum : uint32_t {
115typedef enum : uint8_t {
129typedef enum : uint16_t {
193 __asm__
volatile(
"wfi");
228 k_q16_pi = 205887ULL,
229 k_q16_two_pi = 411775ULL,
230 k_q16_5_pi_sq = 3236018ULL,
231 k_q16_one = 65536ULL,
232 k_q16_numer_k = 16ULL,
233 k_q16_denom_k = 4ULL,
246 const uint64_t pi_minus_x = k_q16_pi - x;
247 const uint64_t numer = k_q16_numer_k * x * pi_minus_x;
248 const uint64_t denom_part = k_q16_denom_k * x * pi_minus_x;
249 const uint64_t denom = k_q16_5_pi_sq - denom_part;
250 const uint64_t sin_q16 = (denom > 0ULL) ? (numer / denom) : 0ULL;
251 const uint64_t scaled = (sin_q16 * half_period) / k_q16_one;
252 uint64_t duty = neg ? (half_period - scaled) : (half_period + scaled);
253 if (duty > period_u64) {
324 .output_enable =
true,
329 const uint8_t channels[k_phase_count] = {
334 for (uint8_t i = 0U; i < k_phase_count; i++) {
366 uint32_t cpuclk0_hz = 0U;
491 k_ascii_zero = 0x30U,
495 uint8_t tmp[k_max_digits];
498 buf[0] = k_ascii_zero;
502 tmp[n] = (uint8_t)(k_ascii_zero + (uint8_t)(value % k_radix));
506 for (uint32_t i = 0U; i < n; i++) {
507 buf[i] = tmp[n - 1U - i];
539 uint8_t digits[k_dec_buf];
613 uint32_t print_accum_ms = 0U;
616 uint32_t u_duty = 0U;
617 uint32_t v_duty = 0U;
618 uint32_t w_duty = 0U;
void main(void)
Secure fallback main entry point.
static uint16_t s_motor_3phase_step
Current sine-table phase index (advances each update tick).
static void internal_motor_3phase_print_duty(uint32_t u_duty, uint32_t v_duty, uint32_t w_duty)
Print "duty UVW <u> <v> <w>\\r\\n" over SCI8.
static const ra8_port_pin_t s_motor_3phase_pin_v
static const ra8_port_pin_t s_motor_3phase_pin_u
Placeholder pin identifiers for the three GTIOCnA outputs.
static void internal_motor_3phase_init_pwm(void)
Open the GPT three-phase block, configure pins, prime duty.
static const ra8_port_pin_t s_motor_3phase_pin_w
static ra8_err_t internal_motor_3phase_pin_configure_all(void)
Configure GTIOR for the three GTIOCnA outputs (active high).
static const uint8_t s_motor_3phase_msg_prefix[]
Diagnostic banner emitted every 100 ms.
static void internal_motor_3phase_advance(uint32_t *out_u, uint32_t *out_v, uint32_t *out_w)
Advance the U/V/W phase by one update tick.
static uint32_t internal_motor_3phase_u32_to_dec(uint32_t value, uint8_t *buf)
Convert a 32-bit unsigned integer into ASCII decimal.
motor_3phase_sine_t
Sine LUT size and step bookkeeping.
@ k_motor_3phase_sine_size
Motor 3phase sine size.
@ k_motor_3phase_phase_120
256 / 3 ~= 85.3 (truncated).
@ k_motor_3phase_phase_240
2 * 256 / 3 ~= 170.6.
@ k_motor_3phase_sine_mask
Motor 3phase sine mask.
motor_3phase_config_t
Compile-time settings for the three-phase motor demo.
@ k_motor_3phase_revolution_ms
Motor 3phase revolution ms.
@ k_motor_3phase_half_period
Motor 3phase half period.
@ k_motor_3phase_baud
Motor 3phase baud.
@ k_motor_3phase_print_period
Motor 3phase print period.
@ k_motor_3phase_dead_time
Motor 3phase dead time.
@ k_motor_3phase_update_ms
Motor 3phase update ms.
@ k_motor_3phase_period
Motor 3phase period.
static void internal_motor_3phase_panic_halt(void)
Halt forever in WFI – used as a panic stop on init failure.
motor_3phase_channel_t
Channel assignments for U/V/W phases.
@ k_motor_3phase_ch_u
Motor 3phase channel u.
@ k_motor_3phase_ch_v
Motor 3phase channel v.
@ k_motor_3phase_ch_w
Motor 3phase channel w.
static ra8_err_t internal_motor_3phase_pins_init(void)
Route the three GTIOC pins.
static void internal_motor_3phase_init_clocks_and_led(void)
Bring CGC + SysTick + LED1 up.
static const uint8_t s_motor_3phase_msg_sep[]
static void internal_motor_3phase_init_console(void)
Open the J-Link OB console (SCI8 @ 115200 8N1).
static const uint8_t s_motor_3phase_msg_eol[]
static void internal_motor_3phase_build_sine(void)
Build the sine LUT using a Bhaskara I approximation.
static uint32_t s_motor_3phase_sine[k_motor_3phase_sine_size]
Compile-time sine table, normalised to 0..period.
Annotation-attribute framework macros for ra8-firmware.
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
ra8_err_t ra8_board_led_toggle(ra8_board_led_id_t led)
Toggle led's output state.
ra8_err_t ra8_board_led_init(ra8_board_led_id_t led)
Configure led as a digital output, initial level low (off).
@ k_ra8_board_led1
LED1, BLUE, P600 (jumper E27).
ra8_err_t ra8_board_uart_console_write(const uint8_t *data, size_t len)
Polled blocking write to the J-Link OB VCOM console.
ra8_err_t ra8_board_uart_console_init(uint32_t baud)
Configure SCI8 + PD02/PD03 as the debug-console UART.
Boot entry points shared between a vector table and its startup code.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
@ k_ra8_clock_id_cpuclk0
Cortex-M85 CPUCLK0.
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
PSEL codes for peripheral pin routing on the RA8D2.
@ k_ra8_psel_gpt0
00011b: GPT timer I/O (GTIOCnA/B).
Full-featured General PWM Timer (GPT) driver.
ra8_err_t ra8_gpt_pwm_pin_configure(uint8_t channel, ra8_gpt_pwm_pin_t pin, const ra8_gpt_pwm_pin_cfg_t *cfg)
Configure GTIOR for one PWM output pin.
@ k_ra8_gpt_stop_low
OnDFLT = 0 -> stop level low.
ra8_err_t ra8_gpt_dead_time_set(uint8_t channel, uint32_t rising_dt, uint32_t falling_dt)
Programme the dead-time value pair for complementary PWM.
@ k_ra8_gpt_pin_a
GTIOCnA – compare register A path.
@ k_ra8_gpt_disable_high_z
POEG fault -> Hi-Z.
ra8_err_t ra8_gpt_three_phase_set_duty(uint32_t u_duty, uint32_t v_duty, uint32_t w_duty)
Atomically update U/V/W compare values via the shadow buffer.
@ k_ra8_gpt_mode_triangle_pwm
Triangle-wave PWM symmetric.
ra8_err_t ra8_gpt_three_phase_open(const ra8_gpt_three_phase_cfg_t *cfg)
Open three GPT channels as a phase-synchronized U/V/W triple.
@ k_ra8_gpt_pol_active_high
Output is high while duty < count.
@ k_ra8_gpt_ps_div_1
PCLKD / 1.
NVIC + ICU IELSR allocator.
void ra8_isr_globals_enable(void)
Globally enable maskable interrupts (PRIMASK = 0).
Ref-counted Module Stop Control wrapper for the RA8D2.
ra8_err_t ra8_mstp_init(void)
Re-establish the ra8_mstp ref-count table from current hardware state.
Typed Port / Pin Constants for the RA8D2 IOPORT Module.
ra8_port_pin_t
Packed (port << 8) | pin pin identifier.
@ k_ra8_port_4
RA8 port 4.
#define RA8_PIN(port, pin)
Build a ra8_port_pin_t from explicit port / pin indices.
@ k_ra8_pin_10
RA8 pin 10.
High-level GPIO helpers on top of the PORT + PFS register layer.
ra8_err_t ra8_pfs_route_peripheral(ra8_port_pin_t pin, ra8_psel_t psel, const char *owner)
Route a pin to a non-IRQ peripheral function via PFS.PSEL.
SysTick-based tick counter, delay and timestamp helpers.
ra8_err_t ra8_time_init(uint32_t cpu_hz)
Initialise SysTick for a 1 kHz tick interrupt.
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Configuration descriptor for ra8_gpt_pwm_pin_configure.
Configuration descriptor for ra8_gpt_three_phase_open.