Full-featured General PWM Timer (GPT) driver. More...

#include <stdint.h>
#include "ra8_dma.h"
#include "ra8_err.h"

Include dependency graph for ra8_gpt.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	ra8_gpt_cfg_t
	Configuration descriptor for ra8_gpt_init. More...
struct	ra8_gpt_pwm_pin_cfg_t
	Configuration descriptor for ra8_gpt_pwm_pin_configure. More...
struct	ra8_gpt_three_phase_cfg_t
	Configuration descriptor for ra8_gpt_three_phase_open. More...

Typedefs
typedef void(*	ra8_gpt_event_fn_t) (void *ctx, uint32_t status_mask)
	GPT IRQ event callback signature.

Enumerations
enum	ra8_gpt_mode_t : uint8_t { k_ra8_gpt_mode_saw_pwm = 0U , k_ra8_gpt_mode_saw_one_shot = 1U , k_ra8_gpt_mode_triangle_pwm = 4U , k_ra8_gpt_mode_triangle_pwm2 = 5U , k_ra8_gpt_mode_triangle_pwm3 = 6U }
	GPT counter-mode selection (GTCR.MD field). More...
enum	ra8_gpt_prescaler_t : uint8_t { k_ra8_gpt_ps_div_1 = 0U , k_ra8_gpt_ps_div_4 = 1U , k_ra8_gpt_ps_div_16 = 2U , k_ra8_gpt_ps_div_64 = 3U , k_ra8_gpt_ps_div_256 = 4U , k_ra8_gpt_ps_div_1024 = 5U }
	GTCR.TPCS clock prescaler. More...
enum	ra8_gpt_status_mask_t : uint32_t { k_ra8_gpt_status_none = 0x00000000UL , k_ra8_gpt_status_ccra = 0x00000001UL , k_ra8_gpt_status_ccrb = 0x00000002UL , k_ra8_gpt_status_overflow = 0x00000040UL , k_ra8_gpt_status_underflow = 0x00000080UL }
	Bit mask of GPT status flags (GTST register subset). More...
enum	ra8_gpt_ccr_sel_t : uint8_t { k_ra8_gpt_ccr_a = 0U , k_ra8_gpt_ccr_b = 1U }
	Selector for ra8_gpt_set_duty. More...
enum	ra8_gpt_pwm_pin_t : uint8_t { k_ra8_gpt_pin_a = 0U , k_ra8_gpt_pin_b = 1U }
	Selector for the GTIOCnA / GTIOCnB PWM output pins. More...
enum	ra8_gpt_pwm_polarity_t : uint8_t { k_ra8_gpt_pol_active_high = 0U , k_ra8_gpt_pol_active_low = 1U }
	Output polarity for ra8_gpt_pwm_pin_configure. More...
enum	ra8_gpt_pwm_stop_level_t : uint8_t { k_ra8_gpt_stop_low = 0U , k_ra8_gpt_stop_high = 1U }
	Pin level when the timer is stopped. More...
enum	ra8_gpt_pwm_disable_t : uint8_t { k_ra8_gpt_disable_none = 0U , k_ra8_gpt_disable_high_z = 1U , k_ra8_gpt_disable_drive_low = 2U , k_ra8_gpt_disable_drive_hi = 3U }
	Output-disable-on-POEG-fault behaviour (GTIOR.OADF / OBDF). More...
enum	ra8_gpt_three_phase_idx_t : uint8_t { k_ra8_gpt_three_phase_u = 0U , k_ra8_gpt_three_phase_v = 1U , k_ra8_gpt_three_phase_w = 2U , k_ra8_gpt_three_phase_count = 3U }
	Index into ra8_gpt_three_phase_cfg_t::channels for U/V/W. More...

Functions
ra8_err_t	ra8_gpt_init (uint8_t channel, const ra8_gpt_cfg_t *cfg)
	Initialise a GPT channel with a full config descriptor.
ra8_err_t	ra8_gpt_deinit (uint8_t channel)
	Tear down a channel (stop + MSTP release).
ra8_err_t	ra8_gpt_start_free_run (uint8_t channel, uint32_t period)
	Configure a GPT channel as a free-running up-counter.
ra8_err_t	ra8_gpt_stop (uint8_t channel)
	Stop a GPT channel.
ra8_err_t	ra8_gpt_read (uint8_t channel, uint32_t *out)
	Read the current counter value.
ra8_err_t	ra8_gpt_set_period (uint8_t channel, uint32_t period)
	Change the GPT period (GTPR / GTPBR) at runtime.
ra8_err_t	ra8_gpt_set_duty (uint8_t channel, ra8_gpt_ccr_sel_t which, uint32_t value)
	Change one compare register (GTCCRA / GTCCRB) at runtime.
ra8_err_t	ra8_gpt_period_set (uint8_t channel, uint32_t period_counts)
	Update the GPT period via the shadow buffer (GTPBR).
ra8_err_t	ra8_gpt_duty_cycle_set (uint8_t channel, ra8_gpt_pwm_pin_t pin, uint32_t compare_counts)
	Update one PWM compare value via the shadow buffer.
ra8_err_t	ra8_gpt_counter_set (uint8_t channel, uint32_t value)
	Force GTCNT to value (timer must be stopped).
ra8_err_t	ra8_gpt_pwm_pin_configure (uint8_t channel, ra8_gpt_pwm_pin_t pin, const ra8_gpt_pwm_pin_cfg_t *cfg)
	Configure GTIOR for one PWM output pin.
ra8_err_t	ra8_gpt_dead_time_set (uint8_t channel, uint32_t rising_dt, uint32_t falling_dt)
	Programme the dead-time value pair for complementary PWM.
ra8_err_t	ra8_gpt_three_phase_open (const ra8_gpt_three_phase_cfg_t *cfg)
	Open three GPT channels as a phase-synchronized U/V/W triple.
ra8_err_t	ra8_gpt_three_phase_set_duty (uint32_t u_duty, uint32_t v_duty, uint32_t w_duty)
	Atomically update U/V/W compare values via the shadow buffer.
ra8_err_t	ra8_gpt_three_phase_close (void)
	Stop and tear down the three U/V/W channels.
ra8_err_t	ra8_gpt_get_status (uint8_t channel, uint32_t *out_mask)
	Read GTST overflow / underflow / compare flags.
ra8_err_t	ra8_gpt_clear_status (uint8_t channel, uint32_t mask)
	Clear GTST flag bits (write-0 to clear).
ra8_err_t	ra8_gpt_attach_handler (uint8_t channel, ra8_gpt_event_fn_t fn, void *ctx)
	Attach a GPT event callback for a channel.
ra8_err_t	ra8_gpt_enter_stop (uint8_t channel)
	Put a channel into MSTP-gated stop.
ra8_err_t	ra8_gpt_exit_stop (uint8_t channel)
	Exit MSTP-gated stop.
ra8_err_t	ra8_gpt_write_dma (uint8_t channel, const uint32_t periods, uint16_t count, ra8_dma_complete_fn_t on_complete, void ctx, uint8_t *out_dma_channel)
	Stream a buffer of period values into GPT GTPR via DMA.
ra8_err_t	ra8_gpt_read_dma (uint8_t channel, uint32_t out_counts, uint16_t count, ra8_dma_complete_fn_t on_complete, void ctx, uint8_t *out_dma_channel)
	Capture a stream of GTCNT values into a buffer via DMA.
void	ra8_gpt_dispatch_ovf (uint8_t channel)
	Dispatch GPT overflow (GTCIV) – clear + fire callback.
void	ra8_gpt_dispatch_und (uint8_t channel)
	Dispatch GPT underflow (GTCIU) – clear + fire callback.
void	ra8_gpt_dispatch_ccra (uint8_t channel)
	Dispatch GPT compare-match A (GTCIA) – clear + fire callback.
void	ra8_gpt_dispatch_ccrb (uint8_t channel)
	Dispatch GPT compare-match B (GTCIB) – clear + fire callback.

Detailed Description

Full-featured General PWM Timer (GPT) driver.

Tag: [Ring 3 / HAL] {World: NS}

full build-out of the RA8D2 GPT peripheral. Extends the free-run stub with: descriptor-based init, deinit, runtime period / duty reconfigure, status flags, interrupt attach / dispatch, power transition.

API surface:

ra8_gpt_init(channel, cfg) – full config + MSTP enable
ra8_gpt_deinit(channel) – stop + MSTP release
ra8_gpt_start_free_run – legacy shim
ra8_gpt_stop – legacy
ra8_gpt_read – legacy
ra8_gpt_set_period – runtime GTPR/GTPBR change
ra8_gpt_set_duty – runtime GTCCR[A/B] change
ra8_gpt_get_status / clear_status – GTST overflow/underflow
ra8_gpt_attach_handler – IRQ callback
ra8_gpt_enter_stop / exit_stop – power transition
ra8_gpt_dispatch_ovf / und / ccra / ccrb – ISR entry points

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_gpt.h.

Typedef Documentation

◆ ra8_gpt_event_fn_t

typedef void(* ra8_gpt_event_fn_t) (void *ctx, uint32_t status_mask)

GPT IRQ event callback signature.

Parameters

[in]	ctx	Caller-supplied context.
[in]	status_mask	OR of k_ra8_gpt_status_* bits.

Definition at line 125 of file ra8_gpt.h.

Enumeration Type Documentation

◆ ra8_gpt_ccr_sel_t

enum ra8_gpt_ccr_sel_t : uint8_t

Selector for ra8_gpt_set_duty.

Enumerator
k_ra8_gpt_ccr_a	GTCCRA.
k_ra8_gpt_ccr_b	GTCCRB.

Definition at line 113 of file ra8_gpt.h.

◆ ra8_gpt_mode_t

enum ra8_gpt_mode_t : uint8_t

GPT counter-mode selection (GTCR.MD field).

Enumerator
k_ra8_gpt_mode_saw_pwm	Saw-wave PWM (up-count).
k_ra8_gpt_mode_saw_one_shot	Saw-wave one-shot.
k_ra8_gpt_mode_triangle_pwm	Triangle-wave PWM symmetric.
k_ra8_gpt_mode_triangle_pwm2	Triangle-wave PWM 1.
k_ra8_gpt_mode_triangle_pwm3	Triangle-wave PWM 2.

Definition at line 53 of file ra8_gpt.h.

◆ ra8_gpt_prescaler_t

enum ra8_gpt_prescaler_t : uint8_t

GTCR.TPCS clock prescaler.

Enumerator
k_ra8_gpt_ps_div_1	PCLKD / 1.
k_ra8_gpt_ps_div_4	PCLKD / 4.
k_ra8_gpt_ps_div_16	PCLKD / 16.
k_ra8_gpt_ps_div_64	PCLKD / 64.
k_ra8_gpt_ps_div_256	PCLKD / 256.
k_ra8_gpt_ps_div_1024	PCLKD / 1024.

Definition at line 65 of file ra8_gpt.h.

◆ ra8_gpt_pwm_disable_t

enum ra8_gpt_pwm_disable_t : uint8_t

Output-disable-on-POEG-fault behaviour (GTIOR.OADF / OBDF).

HUM Ch 22.2.13 "GTIOR" Table 22.18, p 944..946.

Enumerator
k_ra8_gpt_disable_none	POEG fault does not affect pin.
k_ra8_gpt_disable_high_z	POEG fault -> Hi-Z.
k_ra8_gpt_disable_drive_low	POEG fault -> drive low.
k_ra8_gpt_disable_drive_hi	POEG fault -> drive high.

Definition at line 181 of file ra8_gpt.h.

◆ ra8_gpt_pwm_pin_t

enum ra8_gpt_pwm_pin_t : uint8_t

Selector for the GTIOCnA / GTIOCnB PWM output pins.

Used by ra8_gpt_duty_cycle_set and ra8_gpt_pwm_pin_configure. Mirrors FSP gpt_io_pin_t::GPT_IO_PIN_GTIOCA / GPT_IO_PIN_GTIOCB from fsp/ra/fsp/src/r_gpt/r_gpt.c.

HUM Ch 22.2.13 "GTIOR : General PWM Timer I/O Control Register" p 942..946 – bit 8 is OAE (output enable A), bit 24 is OBE.

Enumerator
k_ra8_gpt_pin_a	GTIOCnA – compare register A path.
k_ra8_gpt_pin_b	GTIOCnB – compare register B path.

Definition at line 145 of file ra8_gpt.h.

◆ ra8_gpt_pwm_polarity_t

enum ra8_gpt_pwm_polarity_t : uint8_t

Output polarity for ra8_gpt_pwm_pin_configure.

Active-high writes the GTIOR.GTIOA / GTIOR.GTIOB sub-field with "low at compare match, high at cycle end" (0x9 per HUM Table 22.18, p 944). Active-low writes the inverted pattern (0x6).

Enumerator
k_ra8_gpt_pol_active_high	Output is high while duty < count.
k_ra8_gpt_pol_active_low	Output is low while duty < count.

Definition at line 159 of file ra8_gpt.h.

◆ ra8_gpt_pwm_stop_level_t

enum ra8_gpt_pwm_stop_level_t : uint8_t

Pin level when the timer is stopped.

Maps to GTIOR.OADFLT / GTIOR.OBDFLT (HUM Ch 22.2.13).

Enumerator
k_ra8_gpt_stop_low	OnDFLT = 0 -> stop level low.
k_ra8_gpt_stop_high	OnDFLT = 1 -> stop level high.

Definition at line 170 of file ra8_gpt.h.

◆ ra8_gpt_status_mask_t

enum ra8_gpt_status_mask_t : uint32_t

Bit mask of GPT status flags (GTST register subset).

Bit positions match the GTST register in HUM Ch 22.2.16 "GTST : General PWM Timer Status Register", p 962..964: TCFA = bit 0, TCFB = bit 1, TCFPO = bit 6, TCFPU = bit 7.

Enumerator
k_ra8_gpt_status_none	RA8 GPT status none.
k_ra8_gpt_status_ccra	GTST.TCFA (bit 0).
k_ra8_gpt_status_ccrb	GTST.TCFB (bit 1).
k_ra8_gpt_status_overflow	GTST.TCFPO (bit 6).
k_ra8_gpt_status_underflow	GTST.TCFPU (bit 7).

Definition at line 101 of file ra8_gpt.h.

◆ ra8_gpt_three_phase_idx_t

enum ra8_gpt_three_phase_idx_t : uint8_t

Index into ra8_gpt_three_phase_cfg_t::channels for U/V/W.

Enumerator
k_ra8_gpt_three_phase_u	U-phase channel slot.
k_ra8_gpt_three_phase_v	V-phase channel slot.
k_ra8_gpt_three_phase_w	W-phase channel slot.
k_ra8_gpt_three_phase_count	Number of phases.

Definition at line 215 of file ra8_gpt.h.

Function Documentation

◆ ra8_gpt_attach_handler()

ra8_err_t ra8_gpt_attach_handler	(	uint8_t	channel,
		ra8_gpt_event_fn_t	fn,
		void *	ctx )

nodiscard

Attach a GPT event callback for a channel.

Parameters

[in]	channel	GPT channel.
[in]	fn	Callback fired on ISR dispatch.
[in]	ctx	Context passed to the callback.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 429 of file ra8_gpt.c.

References k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, k_ra8_ok, and s_gpt_state.

◆ ra8_gpt_clear_status()

ra8_err_t ra8_gpt_clear_status	(	uint8_t	channel,
		uint32_t	mask )

nodiscard

Clear GTST flag bits (write-0 to clear).

Since: 0.1.0

Definition at line 418 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTST, k_ra8_gpt_gtst_mask, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by gpt_ecc_service_capture(), and internal_wait_ovf().

◆ ra8_gpt_counter_set()

ra8_err_t ra8_gpt_counter_set	(	uint8_t	channel,
		uint32_t	value )

nodiscard

Force GTCNT to value (timer must be stopped).

Mirrors FSP R_GPT_CounterSet – the underlying register is not safe to write while the counter is running, so the call rejects any channel whose GTCR.CST bit is set.

Parameters

[in]	channel	GPT channel 0..13.
[in]	value	New GTCNT value.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Counter updated.
k_ra8_err_null_ptr	channel out of range.
k_ra8_err_invalid_state	Counter is currently running.

Precondition: Timer counter is stopped (GTCR.CST == 0).; IRQs masked or single-threaded init context.

Postcondition: GTCNT holds value.; GTCR.CST is unchanged.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.19 "GTCNT : General PWM Timer Counter", p 980..981.

Definition at line 637 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCNT, r_gpt_channel_regs_t::GTCR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_state, k_ra8_gpt_gtcr_cst_mask, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_dead_time_set()

ra8_err_t ra8_gpt_dead_time_set	(	uint8_t	channel,
		uint32_t	rising_dt,
		uint32_t	falling_dt )

nodiscard

Programme the dead-time value pair for complementary PWM.

Writes GTDVU (rising-edge dead-time) and GTDVD (falling-edge dead-time) and asserts GTDTCR.TDE (dead-time enable) iff at least one of the two values is non-zero. Mirrors the dead-time branch of FSP gpt_hardware_initialize.

Parameters

[in]	channel	GPT channel 0..13.
[in]	rising_dt	Dead-time count for the rising edge (GTDVU).
[in]	falling_dt	Dead-time count for the falling edge (GTDVD).

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Dead-time programmed.
k_ra8_err_null_ptr	channel out of range.

Precondition: Channel previously initialized via ra8_gpt_init.; IRQs masked or single-threaded init context.

Postcondition: GTDVU == rising_dt and GTDVD == falling_dt.; GTDTCR.TDE bit is set iff either input is non-zero.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.27 "GTDTCR : General PWM Timer Dead Time Control Register", p 998..999. Ch 22.2.28 "GTDVU/GTDVD", p 1000..1001.

Definition at line 716 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTDTCR, r_gpt_channel_regs_t::GTDVD, r_gpt_channel_regs_t::GTDVU, r_gpt_channel_regs_t::GTWP, k_ra8_gpt_gtdtcr_tde, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by internal_motor_3phase_pin_configure_all().

◆ ra8_gpt_deinit()

ra8_err_t ra8_gpt_deinit ( uint8_t channel )

nodiscard

Tear down a channel (stop + MSTP release).

Since: 0.1.0

Definition at line 365 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCR, r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTWP, k_ra8_gpt_gtstp_stop, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), ra8_mstp_disable(), s_gpt_mstp_table, s_gpt_state, and s_tag.

Referenced by internal_three_phase_init_subs(), and ra8_gpt_three_phase_close().

◆ ra8_gpt_dispatch_ccra()

void ra8_gpt_dispatch_ccra ( uint8_t channel )

Dispatch GPT compare-match A (GTCIA) – clear + fire callback.

Parameters

[in] channel GPT channel.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 913 of file ra8_gpt.c.

References internal_dispatch(), and k_ra8_gpt_status_ccra.

◆ ra8_gpt_dispatch_ccrb()

void ra8_gpt_dispatch_ccrb ( uint8_t channel )

Dispatch GPT compare-match B (GTCIB) – clear + fire callback.

Parameters

[in] channel GPT channel.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 919 of file ra8_gpt.c.

References internal_dispatch(), and k_ra8_gpt_status_ccrb.

◆ ra8_gpt_dispatch_ovf()

void ra8_gpt_dispatch_ovf ( uint8_t channel )

Dispatch GPT overflow (GTCIV) – clear + fire callback.

Parameters

[in] channel GPT channel.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 901 of file ra8_gpt.c.

References internal_dispatch(), and k_ra8_gpt_status_overflow.

◆ ra8_gpt_dispatch_und()

void ra8_gpt_dispatch_und ( uint8_t channel )

Dispatch GPT underflow (GTCIU) – clear + fire callback.

Parameters

[in] channel GPT channel.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 907 of file ra8_gpt.c.

References internal_dispatch(), and k_ra8_gpt_status_underflow.

◆ ra8_gpt_duty_cycle_set()

ra8_err_t ra8_gpt_duty_cycle_set	(	uint8_t	channel,
		ra8_gpt_pwm_pin_t	pin,
		uint32_t	compare_counts )

nodiscard

Update one PWM compare value via the shadow buffer.

Writes compare_counts into GTCCRC (for k_ra8_gpt_pin_a) or GTCCRE (for k_ra8_gpt_pin_b). Per FSP R_GPT_DutyCycleSet the buffer registers are swapped into GTCCRA/GTCCRB at the next cycle end, so PWM transitions are glitch-free. The GTBER.CCRA / GTBER.CCRB single-buffer enable bits are also asserted so the swap actually happens.

Parameters

[in]	channel	GPT channel 0..13.
[in]	pin	Which output pin – A or B.
[in]	compare_counts	New compare value (must be <= period).

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Compare buffer programmed.
k_ra8_err_invalid_arg	pin not in ra8_gpt_pwm_pin_t.
k_ra8_err_null_ptr	channel out of range.

Precondition: Channel previously initialized via ra8_gpt_init.; Caller has ensured compare_counts <= GTPR.

Postcondition: GTCCRC / GTCCRE holds the new value.; GTBER buffer-enable bit for the selected pin is asserted.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.20 "GTCCRA..F : General PWM Timer Compare/Capture Registers", p 982..984. Ch 22.2.17 "GTBER : General PWM Timer Buffer Enable Register", p 965..968.

Definition at line 613 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTBER, r_gpt_channel_regs_t::GTCCR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_gpt_ccr_idx_c, k_ra8_gpt_ccr_idx_e, k_ra8_gpt_gtber_ccra_single, k_ra8_gpt_gtber_ccrb_single, k_ra8_gpt_pin_a, k_ra8_gpt_pin_b, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, pin, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_enter_stop()

ra8_err_t ra8_gpt_enter_stop ( uint8_t channel )

nodiscard

Put a channel into MSTP-gated stop.

Since: 0.1.0

Definition at line 439 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, k_ra8_gpt_gtstp_stop, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, ra8_gpt(), ra8_mstp_disable(), and s_gpt_mstp_table.

◆ ra8_gpt_exit_stop()

ra8_err_t ra8_gpt_exit_stop ( uint8_t channel )

nodiscard

Exit MSTP-gated stop.

Since: 0.1.0

Definition at line 453 of file ra8_gpt.c.

References k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, ra8_mstp_enable(), and s_gpt_mstp_table.

◆ ra8_gpt_get_status()

ra8_err_t ra8_gpt_get_status	(	uint8_t	channel,
		uint32_t *	out_mask )

nodiscard

Read GTST overflow / underflow / compare flags.

Parameters

[in]	channel	GPT channel.
[out]	out_mask	OR of k_ra8_gpt_status_*.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 408 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTST, k_ra8_gpt_gtst_mask, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by gpt_ecc_service_capture(), and internal_wait_ovf().

◆ ra8_gpt_init()

ra8_err_t ra8_gpt_init	(	uint8_t	channel,
		const ra8_gpt_cfg_t *	cfg )

nodiscard

Initialise a GPT channel with a full config descriptor.

Parameters

[in]	channel	GPT channel (0..13).
[in]	cfg	Non-NULL configuration descriptor.

Returns: ra8_err_t error code.

Precondition: IRQs masked or single-threaded init context.; ra8_mstp_init has been called.

Postcondition: On success, GTCR + GTPR + GTCCR are programmed and (if cfg->auto_start) GTSTR is set.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 329 of file ra8_gpt.c.

Referenced by gpt_ecc_timers_or_halt(), internal_arm(), internal_arm_channel(), internal_gpt_irq_demo_arm(), internal_gpt_pwm_demo_arm(), internal_poeg_demo_arm_gpt(), internal_setup_or_halt(), internal_three_phase_init_subs(), ra8_board_camera_xclk_start(), and ra8_nsc_gpt_init().

◆ ra8_gpt_period_set()

ra8_err_t ra8_gpt_period_set	(	uint8_t	channel,
		uint32_t	period_counts )

nodiscard

Update the GPT period via the shadow buffer (GTPBR).

Writes period_counts to GTPBR; on the next overflow the timer loads GTPBR into GTPR. If the counter is currently stopped the value is also written into GTPR immediately and the counter is cleared so the next ra8_gpt_set_period style call has the same starting point as a fresh ra8_gpt_init. Mirrors FSP R_GPT_PeriodSet from fsp/ra/fsp/src/r_gpt/r_gpt.c.

Parameters

[in]	channel	GPT channel 0..13.
[in]	period_counts	New period in counter ticks.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Period buffer programmed.
k_ra8_err_null_ptr	channel out of range.

Precondition: Channel previously initialized via ra8_gpt_init.; IRQs masked or single-threaded init context.

Postcondition: GTPBR holds period_counts.; On the next overflow GTPR is reloaded from GTPBR.

Note: Thread safety: not thread-safe.

See also: ra8_gpt_set_period() Legacy single-shot variant (no buffer).

Since: 0.1.0

HUM:: Ch 22.2.21 "GTPR : General PWM Timer Cycle Setting Register", p 985..986.

Definition at line 595 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCNT, r_gpt_channel_regs_t::GTCR, r_gpt_channel_regs_t::GTPBR, r_gpt_channel_regs_t::GTPR, r_gpt_channel_regs_t::GTWP, k_ra8_gpt_gtcr_cst_mask, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_pwm_pin_configure()

ra8_err_t ra8_gpt_pwm_pin_configure	(	uint8_t	channel,
		ra8_gpt_pwm_pin_t	pin,
		const ra8_gpt_pwm_pin_cfg_t *	cfg )

nodiscard

Configure GTIOR for one PWM output pin.

Programmes the polarity, output-enable, stop level, and output-disable-on-POEG-fault behaviour for either GTIOCnA or GTIOCnB. Mirrors the GTIOR-write portion of FSP R_GPT_OutputEnable / R_GPT_OutputDisable and the PWM setup logic in gpt_hardware_initialize.

Parameters

[in]	channel	GPT channel 0..13.
[in]	pin	Which output pin – A or B.
[in]	cfg	Non-NULL configuration descriptor.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Pin configured.
k_ra8_err_null_ptr	channel out of range or cfg NULL.
k_ra8_err_invalid_arg	pin not in ra8_gpt_pwm_pin_t.

Precondition: Channel previously initialized via ra8_gpt_init.; IRQs masked or single-threaded init context.

Postcondition: GTIOR fields for the selected pin reflect cfg.; GTIOR fields for the other pin are preserved.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.13 "GTIOR : General PWM Timer I/O Control Register", p 942..946 – bit 8 OAE, bit 24 OBE, bit 6 OADFLT, bit 22 OBDFLT, bits [9..10] OADF, bits [25..26] OBDF, bits [0..4] GTIOA[4:0], bits [16..20] GTIOB[4:0].

Definition at line 678 of file ra8_gpt.c.

References ra8_gpt_pwm_pin_cfg_t::disable_on_fault, r_gpt_channel_regs_t::GTIOR, r_gpt_channel_regs_t::GTWP, internal_gtio_pattern(), k_ra8_err_invalid_arg, k_ra8_gpt_gtioa_mask, k_ra8_gpt_gtioa_shift, k_ra8_gpt_gtiob_mask, k_ra8_gpt_gtiob_shift, k_ra8_gpt_oadf_mask, k_ra8_gpt_oadf_shift, k_ra8_gpt_oadflt_mask, k_ra8_gpt_oadflt_shift, k_ra8_gpt_oae_mask, k_ra8_gpt_obdf_mask, k_ra8_gpt_obdf_shift, k_ra8_gpt_obdflt_mask, k_ra8_gpt_obdflt_shift, k_ra8_gpt_obe_mask, k_ra8_gpt_pin_a, k_ra8_gpt_pin_b, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, ra8_gpt_pwm_pin_cfg_t::output_enable, pin, ra8_gpt_pwm_pin_cfg_t::polarity, RA8_CHECK_NULL_PTR, ra8_gpt(), s_tag, and ra8_gpt_pwm_pin_cfg_t::stop_level.

Referenced by internal_motor_3phase_pin_configure_all(), and ra8_board_camera_xclk_start().

◆ ra8_gpt_read()

ra8_err_t ra8_gpt_read	(	uint8_t	channel,
		uint32_t *	out )

nodiscard

Read the current counter value.

Parameters

[in]	channel	GPT channel (0..13).
[out]	out	Receive counter value.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 314 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCNT, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by cam_run(), internal_poeg_demo_cycle(), internal_read(), main(), ra8_nsc_gpt_read(), and timer_demo_one_capture().

◆ ra8_gpt_read_dma()

ra8_err_t ra8_gpt_read_dma	(	uint8_t	channel,
		uint32_t *	out_counts,
		uint16_t	count,
		ra8_dma_complete_fn_t	on_complete,
		void *	ctx,
		uint8_t *	out_dma_channel )

nodiscard

Capture a stream of GTCNT values into a buffer via DMA.

Programmes the ra8_dma substrate to copy count 32-bit counter snapshots from the channel's GTCNT register into out_counts[]. This is the "capture streaming" DMA RX path from the roadmap note – the driver samples GTCNT on each ELC trigger and stores the value, so the host sees the full capture sequence without ISR overhead.

Parameters

[in]	channel	GPT channel 0..13.
[out]	out_counts	Destination counter buffer. Must outlive the transfer.
[in]	count	Number of samples; non-zero.
[in]	on_complete	Completion callback. May be NULL.
[in]	ctx	Context passed to on_complete.
[out]	out_dma_channel	Allocated DMAC channel on success.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Transfer armed.
k_ra8_err_null_ptr	out_counts / out_dma_channel NULL.
k_ra8_err_invalid_arg	Channel or count invalid.
k_ra8_err_no_mem	All DMAC channels in use.
k_ra8_err_hw_error	ra8_dma_request failed.

Precondition: Channel previously initialized via ra8_gpt_init.; ra8_dma_init has been called.

Postcondition: On success, DMAC channel is armed.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 493 of file ra8_gpt.c.

References ra8_dma_request_t::count, ra8_dma_request_t::ctx, ra8_dma_request_t::dst_addr, ra8_dma_request_t::dst_inc, r_gpt_channel_regs_t::GTCNT, k_ra8_dmac_width_word, k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, ra8_dma_request_t::on_complete, RA8_CHECK_NULL_PTR, ra8_dma_request(), ra8_gpt(), s_tag, ra8_dma_request_t::src_addr, ra8_dma_request_t::src_inc, ra8_dma_request_t::trigger, and ra8_dma_request_t::width.

◆ ra8_gpt_set_duty()

ra8_err_t ra8_gpt_set_duty	(	uint8_t	channel,
		ra8_gpt_ccr_sel_t	which,
		uint32_t	value )

nodiscard

Change one compare register (GTCCRA / GTCCRB) at runtime.

Parameters

[in]	channel	GPT channel.
[in]	which	Which compare register.
[in]	value	New compare value.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 394 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCCR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_gpt_ccr_b, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by main().

◆ ra8_gpt_set_period()

ra8_err_t ra8_gpt_set_period	(	uint8_t	channel,
		uint32_t	period )

nodiscard

Change the GPT period (GTPR / GTPBR) at runtime.

Parameters

[in]	channel	GPT channel.
[in]	period	New GTPR value.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 382 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTPBR, r_gpt_channel_regs_t::GTPR, r_gpt_channel_regs_t::GTWP, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_start_free_run()

ra8_err_t ra8_gpt_start_free_run	(	uint8_t	channel,
		uint32_t	period )

nodiscard

Configure a GPT channel as a free-running up-counter.

Parameters

[in]	channel	GPT channel (0..13).
[in]	period	Period in timer ticks (write to GTPR).

Returns: ra8_err_t error code.

Note: The counter runs from PCLKD (or a configurable source) with no prescaler. The caller is responsible for choosing a sensible period value given the current PCLKD.

Since: 0.1.0

Definition at line 274 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCNT, r_gpt_channel_regs_t::GTCR, r_gpt_channel_regs_t::GTPR, r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTSTR, r_gpt_channel_regs_t::GTWP, internal_gpt_clock_block_init(), k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), ra8_log_info_val, ra8_mstp_enable(), RA8_RETURN_ON_ERROR, s_gpt_mstp_table, and s_tag.

Referenced by internal_gpt_irq_demo_arm(), main(), and timer_demo_setup_or_halt().

◆ ra8_gpt_stop()

ra8_err_t ra8_gpt_stop ( uint8_t channel )

nodiscard

Stop a GPT channel.

Parameters

[in] channel GPT channel (0..13).

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 303 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTWP, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_three_phase_close()

ra8_err_t ra8_gpt_three_phase_close ( void )

nodiscard

Stop and tear down the three U/V/W channels.

Stops the three channels via a single GTSTP write and calls ra8_gpt_deinit on each. Mirrors FSP R_GPT_THREE_PHASE_Stop + R_GPT_THREE_PHASE_Close.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	All three channels closed.
k_ra8_err_invalid_state	ra8_gpt_three_phase_open not called.

Precondition: ra8_gpt_three_phase_open returned k_ra8_ok.; IRQs masked or single-threaded shutdown context.

Postcondition: All three channels are stopped and MSTP-released.; Three-phase state is marked closed.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 860 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_state, k_ra8_gpt_three_phase_count, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, ra8_gpt(), ra8_gpt_deinit(), and s_three_phase.

◆ ra8_gpt_three_phase_open()

ra8_err_t ra8_gpt_three_phase_open ( const ra8_gpt_three_phase_cfg_t * cfg )

nodiscard

Open three GPT channels as a phase-synchronized U/V/W triple.

Calls ra8_gpt_init on each of the three channels in cfg->channels with the same mode, prescaler, and period. After all three are configured, the U-channel's GTSTR is written with a bitmask covering all three channel positions so they start on the same PCLKD edge. Mirrors FSP R_GPT_THREE_PHASE_Open + R_GPT_THREE_PHASE_Start.

Parameters

[in] cfg Non-NULL three-phase configuration descriptor.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	All three channels opened and started.
k_ra8_err_null_ptr	cfg NULL.
k_ra8_err_invalid_arg	Any channel id out of range or already open.

Precondition: ra8_mstp_init has been called.; IRQs masked or single-threaded init context.

Postcondition: All three GPT channels are configured and counting.; Driver-internal three-phase state is marked open.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.2 "GTSTR : General PWM Timer Software Start Register", p 901 – writing multiple CSTRTn bits in one access starts those channels synchronously.

Definition at line 799 of file ra8_gpt.c.

References ra8_gpt_three_phase_cfg_t::channels, r_gpt_channel_regs_t::GTSTR, r_gpt_channel_regs_t::GTWP, internal_three_phase_init_subs(), k_ra8_err_invalid_arg, k_ra8_err_invalid_state, k_ra8_gpt_channel_count, k_ra8_gpt_three_phase_count, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), ra8_log_info_val, s_tag, and s_three_phase.

Referenced by internal_gpt_3p_demo_arm(), and internal_motor_3phase_init_pwm().

◆ ra8_gpt_three_phase_set_duty()

ra8_err_t ra8_gpt_three_phase_set_duty	(	uint32_t	u_duty,
		uint32_t	v_duty,
		uint32_t	w_duty )

nodiscard

Atomically update U/V/W compare values via the shadow buffer.

Writes u_duty / v_duty / w_duty into the GTCCRC and GTCCRE shadow buffers of the three channels recorded by ra8_gpt_three_phase_open. The GTBER buffer-enable bit makes the swap into GTCCRA/B happen at the next cycle end, so all three phases update on the same overflow. Mirrors FSP R_GPT_THREE_PHASE_DutyCycleSet.

Parameters

[in]	u_duty	New U-phase compare value.
[in]	v_duty	New V-phase compare value.
[in]	w_duty	New W-phase compare value.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Compare values queued for swap.
k_ra8_err_invalid_state	ra8_gpt_three_phase_open not called.
k_ra8_err_invalid_arg	Any duty value > GTPR.

Precondition: ra8_gpt_three_phase_open returned k_ra8_ok.; All three duty values <= the shared period.

Postcondition: GTCCRC and GTCCRE on each channel hold the new duty.; Three-phase state is still open.

Note: Thread safety: not thread-safe. Recommended to call from a high-priority ISR per FSP r_gpt_three_phase guidance.

Since: 0.1.0

HUM:: Ch 22.2.20 "GTCCRA..F", p 982..984. Ch 22.2.17 "GTBER", p 965.

Definition at line 833 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTBER, r_gpt_channel_regs_t::GTCCR, r_gpt_channel_regs_t::GTPR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_err_invalid_state, k_ra8_gpt_ccr_idx_c, k_ra8_gpt_ccr_idx_e, k_ra8_gpt_gtber_ccra_single, k_ra8_gpt_gtber_ccrb_single, k_ra8_gpt_three_phase_count, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, ra8_gpt(), and s_three_phase.

Referenced by internal_motor_3phase_init_pwm(), and main().

◆ ra8_gpt_write_dma()

ra8_err_t ra8_gpt_write_dma	(	uint8_t	channel,
		const uint32_t *	periods,
		uint16_t	count,
		ra8_dma_complete_fn_t	on_complete,
		void *	ctx,
		uint8_t *	out_dma_channel )

nodiscard

Stream a buffer of period values into GPT GTPR via DMA.

Programmes the ra8_dma substrate to copy count 32-bit period values from periods[] into the channel's GTPR register. This is the "sample streaming" DMA TX path from the roadmap note – the driver pumps a preloaded period sequence into the timer without the CPU touching GTPR each tick.

Parameters

[in]	channel	GPT channel 0..13.
[in]	periods	Source array of 32-bit period values. Must outlive the transfer.
[in]	count	Number of periods; non-zero.
[in]	on_complete	Completion callback. May be NULL.
[in]	ctx	Context passed to on_complete.
[out]	out_dma_channel	Allocated DMAC channel on success.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Transfer armed.
k_ra8_err_null_ptr	periods / out_dma_channel NULL.
k_ra8_err_invalid_arg	Channel or count invalid.
k_ra8_err_no_mem	All DMAC channels in use.
k_ra8_err_hw_error	ra8_dma_request failed.

Precondition: Channel previously initialized via ra8_gpt_init.; ra8_dma_init has been called.

Postcondition: On success, DMAC channel is armed.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 463 of file ra8_gpt.c.

References ra8_dma_request_t::count, ra8_dma_request_t::ctx, ra8_dma_request_t::dst_addr, ra8_dma_request_t::dst_inc, r_gpt_channel_regs_t::GTPR, k_ra8_dmac_width_word, k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, ra8_dma_request_t::on_complete, RA8_CHECK_NULL_PTR, ra8_dma_request(), ra8_gpt(), s_tag, ra8_dma_request_t::src_addr, ra8_dma_request_t::src_inc, ra8_dma_request_t::trigger, and ra8_dma_request_t::width.

Referenced by internal_run_one().

Data Structures

Typedefs

Enumerations

Functions

Detailed Description

Typedef Documentation

◆ ra8_gpt_event_fn_t

Enumeration Type Documentation

◆ ra8_gpt_ccr_sel_t

◆ ra8_gpt_mode_t

◆ ra8_gpt_prescaler_t

◆ ra8_gpt_pwm_disable_t

◆ ra8_gpt_pwm_pin_t

◆ ra8_gpt_pwm_polarity_t

◆ ra8_gpt_pwm_stop_level_t

◆ ra8_gpt_status_mask_t

◆ ra8_gpt_three_phase_idx_t

Function Documentation

◆ ra8_gpt_attach_handler()

◆ ra8_gpt_clear_status()

◆ ra8_gpt_counter_set()

◆ ra8_gpt_dead_time_set()

◆ ra8_gpt_deinit()

◆ ra8_gpt_dispatch_ccra()

◆ ra8_gpt_dispatch_ccrb()

◆ ra8_gpt_dispatch_ovf()

◆ ra8_gpt_dispatch_und()

◆ ra8_gpt_duty_cycle_set()

◆ ra8_gpt_enter_stop()

◆ ra8_gpt_exit_stop()

◆ ra8_gpt_get_status()

◆ ra8_gpt_init()

◆ ra8_gpt_period_set()

◆ ra8_gpt_pwm_pin_configure()

◆ ra8_gpt_read()

◆ ra8_gpt_read_dma()

◆ ra8_gpt_set_duty()

◆ ra8_gpt_set_period()

◆ ra8_gpt_start_free_run()

◆ ra8_gpt_stop()

◆ ra8_gpt_three_phase_close()

◆ ra8_gpt_three_phase_open()

◆ ra8_gpt_three_phase_set_duty()

◆ ra8_gpt_write_dma()