ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_board_ek_ra8d2_camera.c
Go to the documentation of this file.
1
15
16#include <stdint.h>
17
18#include "ra8_board_ek_ra8d2.h"
19#include "ra8_cgc.h"
20#include "ra8_check.h"
21#include "ra8_gpt.h"
22#include "ra8_i2c.h"
23#include "ra8_port_utils.h"
24#include "ra8_time.h"
25
34
39
40typedef enum : uint32_t {
43
57
58/* See the public header for the documented contract. */
60{
61 if (frequency_hz == 0U) {
63 }
64 uint32_t pclkd_hz = 0U;
66 if (err != k_ra8_ok) {
67 return err;
68 }
69 const uint32_t period = pclkd_hz / frequency_hz;
70 if ((period < 2U) || (period > (uint32_t)k_camera_gpt_period_max)) {
72 }
73 const ra8_gpt_cfg_t timer_cfg = {
75 .prescaler = k_ra8_gpt_ps_div_1,
76 .period = period - 1U,
77 .duty_a = period / 2U,
78 .duty_b = 0U,
79 .auto_start = true,
80 };
81 err = ra8_gpt_init((uint8_t)k_camera_xclk_gpt_channel, &timer_cfg);
82 if (err != k_ra8_ok) {
83 return err;
84 }
85 const ra8_gpt_pwm_pin_cfg_t pin_cfg = {
86 .output_enable = true,
87 .polarity = k_ra8_gpt_pol_active_high,
88 .stop_level = k_ra8_gpt_stop_low,
89 .disable_on_fault = k_ra8_gpt_disable_none,
90 };
92 if (err != k_ra8_ok) {
93 return err;
94 }
97 "board.camera.xclk");
98 if (err != k_ra8_ok) {
99 return err;
100 }
103}
104
105/* See the public header for the documented contract. */
111
112/* See the public header for the documented contract. */
114{
115 const uint32_t count =
116 (uint32_t)(sizeof(s_camera_parallel_pins) / sizeof(s_camera_parallel_pins[0]));
117 for (uint32_t i = 0U; i < count; i += 1U) {
118 const ra8_err_t err =
120 if (err != k_ra8_ok) {
121 return err;
122 }
123 }
124 return k_ra8_ok;
125}
126
127/* See the public header for the documented contract. */
129{
132 if (err != k_ra8_ok) {
133 return err;
134 }
136 err = ra8_gpio_write(reset_pin, k_ra8_level_high);
137 if (err != k_ra8_ok) {
138 return err;
139 }
141 return k_ra8_ok;
142}
143
144/* See the public header for the documented contract. */
146ra8_board_camera_sccb_read_reg(void* ctx, uint8_t address, uint16_t reg, uint8_t* out_value)
147{
148 (void)ctx;
149 RA8_CHECK_NULL_PTR(out_value, "board.camera", "read");
150 const uint8_t register_address[k_camera_reg_address_bytes] = {
151 (uint8_t)(reg >> (uint16_t)k_camera_high_byte_shift),
152 (uint8_t)reg,
153 };
155 address,
156 register_address,
157 (uint32_t)sizeof(register_address),
158 out_value,
159 1U);
160}
161
162/* See the public header for the documented contract. */
163ra8_err_t ra8_board_camera_sccb_write_reg(void* ctx, uint8_t address, uint16_t reg, uint8_t value)
164{
165 (void)ctx;
166 const uint8_t payload[k_camera_write_bytes] = {
167 (uint8_t)(reg >> (uint16_t)k_camera_high_byte_shift),
168 (uint8_t)reg,
169 value,
170 };
172 address,
173 payload,
174 (uint32_t)sizeof(payload),
175 true);
176}
177
178/* See the public header for the documented contract. */
179void ra8_board_camera_delay_ms(void* ctx, uint32_t milliseconds)
180{
181 (void)ctx;
182 ra8_delay_ms(milliseconds);
183}
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
@ k_camera_gpt_period_max
Maximum GPT period register value.
ra8_err_t ra8_board_camera_reset(void)
Pulse the J35 camera reset input and leave the sensor released.
static const ra8_port_pin_t s_camera_parallel_pins[]
ra8_err_t ra8_board_camera_sccb_write_reg(void *ctx, uint8_t address, uint16_t reg, uint8_t value)
Write one 16-bit-addressed SCCB register on the J35 camera bus.
ra8_err_t ra8_board_camera_sccb_read_reg(void *ctx, uint8_t address, uint16_t reg, uint8_t *out_value)
Read one 16-bit-addressed SCCB register on the J35 camera bus.
ra8_board_camera_protocol_t
@ k_camera_xclk_gpt_channel
GPT channel driving XCLK.
@ k_camera_sw46_mask
U15 SW4-6 override bit.
@ k_camera_reg_address_bytes
SCCB register-address bytes.
@ k_camera_sw46_output
U15 latch with SW4-6 ON.
@ k_camera_high_byte_shift
Register high-byte shift.
@ k_camera_write_bytes
Address plus value bytes.
ra8_err_t ra8_board_camera_xclk_start(uint32_t frequency_hz)
Start the J35 camera sensor input clock (XCLK) on P501/GTIOC12A.
ra8_err_t ra8_board_camera_route_parallel_pins(void)
Route J35 D[7:0], VSYNC, HSYNC and PCLK to the CEU peripheral.
@ k_camera_reset_high_ms
Reset release interval.
@ k_camera_reset_low_ms
Reset assertion interval.
ra8_err_t ra8_board_camera_select_parallel(void)
Drive only SW4-6 ON through U15, selecting J35 parallel DVP.
void ra8_board_camera_delay_ms(void *ctx, uint32_t milliseconds)
Millisecond delay adapter for transport-independent camera drivers.
@ k_ra8_board_camera_i2c_channel
RIIC1 serves J35 SCCB.
ra8_err_t ra8_board_io_expander_apply_sw4_mask(uint8_t output_byte, uint8_t output_mask)
Override selected SW4 positions while releasing every other position.
@ k_ra8_board_cam_d3
CAM D3, P406 (J41).
@ k_ra8_board_cam_pclk
CAM PCLK, PB04.
@ k_ra8_board_cam_vsync
CAM VSYNC, PB02.
@ k_ra8_board_cam_d7
CAM D7, P703.
@ k_ra8_board_cam_d0
CAM D0, P400.
@ k_ra8_board_cam_hsync
CAM HSYNC, PB03.
@ k_ra8_board_cam_xclk
CAM XCLK, P501.
@ k_ra8_board_cam_d2
CAM D2, P405 (J41).
@ k_ra8_board_cam_d1
CAM D1, P902.
@ k_ra8_board_cam_rst
CAM RST, P709.
@ k_ra8_board_cam_d5
CAM D5, P701.
@ k_ra8_board_cam_d6
CAM D6, P702.
@ k_ra8_board_cam_d4
CAM D4, P700.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
Definition ra8_cgc.c:132
@ k_ra8_clock_id_pclkd
PCLKD.
Definition ra8_cgc.h:76
Validation and Error-Checking Macros for ra8-firmware.
#define RA8_CHECK_NULL_PTR(ptr, tag, message)
Reject nullptr pointer, returning k_ra8_err_null_ptr.
Definition ra8_check.h:243
@ k_ra8_err_invalid_arg
Invalid function argument.
Definition ra8_err.h:152
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
@ k_ra8_psel_gpt0
00011b: GPT timer I/O (GTIOCnA/B).
@ k_ra8_psel_ceu
01111b: CEU camera capture.
Full-featured General PWM Timer (GPT) driver.
ra8_err_t ra8_gpt_pwm_pin_configure(uint8_t channel, ra8_gpt_pwm_pin_t pin, const ra8_gpt_pwm_pin_cfg_t *cfg)
Configure GTIOR for one PWM output pin.
Definition ra8_gpt.c:678
@ k_ra8_gpt_stop_low
OnDFLT = 0 -> stop level low.
Definition ra8_gpt.h:171
@ k_ra8_gpt_pin_a
GTIOCnA – compare register A path.
Definition ra8_gpt.h:146
@ k_ra8_gpt_disable_none
POEG fault does not affect pin.
Definition ra8_gpt.h:182
@ k_ra8_gpt_mode_saw_pwm
Saw-wave PWM (up-count).
Definition ra8_gpt.h:54
@ k_ra8_gpt_pol_active_high
Output is high while duty < count.
Definition ra8_gpt.h:160
ra8_err_t ra8_gpt_init(uint8_t channel, const ra8_gpt_cfg_t *cfg)
Initialise a GPT channel with a full config descriptor.
Definition ra8_gpt.c:329
@ k_ra8_gpt_ps_div_1
PCLKD / 1.
Definition ra8_gpt.h:66
I2C Bus Interface (IIC) controller driver – polling mode.
ra8_err_t ra8_i2c_write(uint8_t channel, uint8_t peripheral_7b, const uint8_t *data, uint32_t len, bool send_stop)
Polling write of len bytes to a 7-bit peripheral address.
Definition ra8_i2c.c:579
ra8_err_t ra8_i2c_transfer(uint8_t channel, uint8_t peripheral_7b, const uint8_t *wr, uint32_t wr_len, uint8_t *rd, uint32_t rd_len)
Combined write-then-RESTART-then-read in one bus transaction.
Definition ra8_i2c.c:726
@ k_ra8_pfs_dscr_high_speed_high
10b: High-speed high drive.
ra8_port_pin_t
Packed (port << 8) | pin pin identifier.
@ k_ra8_level_high
Drive or read 1.
@ k_ra8_level_low
Drive or read 0.
High-level GPIO helpers on top of the PORT + PFS register layer.
ra8_err_t ra8_pfs_set_drive_strength(ra8_port_pin_t pin, ra8_pfs_dscr_t dscr)
Set the output drive strength (PmnPFS.DSCR) of an already-routed pin.
Definition gpio.c:287
ra8_err_t ra8_gpio_output_init(ra8_port_pin_t pin, ra8_level_t init_level)
Configure a pin as a digital output and drive it to an initial level.
Definition gpio.c:88
ra8_err_t ra8_gpio_write(ra8_port_pin_t pin, ra8_level_t level)
Drive a previously-configured output to the given level.
Definition gpio.c:154
ra8_err_t ra8_pfs_route_peripheral(ra8_port_pin_t pin, ra8_psel_t psel, const char *owner)
Route a pin to a non-IRQ peripheral function via PFS.PSEL.
Definition gpio.c:238
SysTick-based tick counter, delay and timestamp helpers.
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Definition ra8_time.c:129
Configuration descriptor for ra8_gpt_init.
Definition ra8_gpt.h:83
Configuration descriptor for ra8_gpt_pwm_pin_configure.
Definition ra8_gpt.h:199