26typedef enum : uint8_t {
35typedef enum : uint32_t {
40typedef enum : uint32_t {
61 if (frequency_hz == 0U) {
64 uint32_t pclkd_hz = 0U;
69 const uint32_t period = pclkd_hz / frequency_hz;
76 .period = period - 1U,
77 .duty_a = period / 2U,
86 .output_enable =
true,
115 const uint32_t count =
117 for (uint32_t i = 0U; i < count; i += 1U) {
157 (uint32_t)
sizeof(register_address),
174 (uint32_t)
sizeof(payload),
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
@ k_camera_gpt_period_max
Maximum GPT period register value.
ra8_err_t ra8_board_camera_reset(void)
Pulse the J35 camera reset input and leave the sensor released.
static const ra8_port_pin_t s_camera_parallel_pins[]
ra8_err_t ra8_board_camera_sccb_write_reg(void *ctx, uint8_t address, uint16_t reg, uint8_t value)
Write one 16-bit-addressed SCCB register on the J35 camera bus.
ra8_err_t ra8_board_camera_sccb_read_reg(void *ctx, uint8_t address, uint16_t reg, uint8_t *out_value)
Read one 16-bit-addressed SCCB register on the J35 camera bus.
ra8_board_camera_protocol_t
@ k_camera_xclk_gpt_channel
GPT channel driving XCLK.
@ k_camera_sw46_mask
U15 SW4-6 override bit.
@ k_camera_reg_address_bytes
SCCB register-address bytes.
@ k_camera_sw46_output
U15 latch with SW4-6 ON.
@ k_camera_high_byte_shift
Register high-byte shift.
@ k_camera_write_bytes
Address plus value bytes.
ra8_err_t ra8_board_camera_xclk_start(uint32_t frequency_hz)
Start the J35 camera sensor input clock (XCLK) on P501/GTIOC12A.
ra8_err_t ra8_board_camera_route_parallel_pins(void)
Route J35 D[7:0], VSYNC, HSYNC and PCLK to the CEU peripheral.
@ k_camera_reset_high_ms
Reset release interval.
@ k_camera_reset_low_ms
Reset assertion interval.
ra8_err_t ra8_board_camera_select_parallel(void)
Drive only SW4-6 ON through U15, selecting J35 parallel DVP.
void ra8_board_camera_delay_ms(void *ctx, uint32_t milliseconds)
Millisecond delay adapter for transport-independent camera drivers.
@ k_ra8_board_camera_i2c_channel
RIIC1 serves J35 SCCB.
ra8_err_t ra8_board_io_expander_apply_sw4_mask(uint8_t output_byte, uint8_t output_mask)
Override selected SW4 positions while releasing every other position.
@ k_ra8_board_cam_d3
CAM D3, P406 (J41).
@ k_ra8_board_cam_pclk
CAM PCLK, PB04.
@ k_ra8_board_cam_vsync
CAM VSYNC, PB02.
@ k_ra8_board_cam_d7
CAM D7, P703.
@ k_ra8_board_cam_d0
CAM D0, P400.
@ k_ra8_board_cam_hsync
CAM HSYNC, PB03.
@ k_ra8_board_cam_xclk
CAM XCLK, P501.
@ k_ra8_board_cam_d2
CAM D2, P405 (J41).
@ k_ra8_board_cam_d1
CAM D1, P902.
@ k_ra8_board_cam_rst
CAM RST, P709.
@ k_ra8_board_cam_d5
CAM D5, P701.
@ k_ra8_board_cam_d6
CAM D6, P702.
@ k_ra8_board_cam_d4
CAM D4, P700.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
@ k_ra8_clock_id_pclkd
PCLKD.
Validation and Error-Checking Macros for ra8-firmware.
#define RA8_CHECK_NULL_PTR(ptr, tag, message)
Reject nullptr pointer, returning k_ra8_err_null_ptr.
@ k_ra8_err_invalid_arg
Invalid function argument.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
@ k_ra8_psel_gpt0
00011b: GPT timer I/O (GTIOCnA/B).
@ k_ra8_psel_ceu
01111b: CEU camera capture.
Full-featured General PWM Timer (GPT) driver.
ra8_err_t ra8_gpt_pwm_pin_configure(uint8_t channel, ra8_gpt_pwm_pin_t pin, const ra8_gpt_pwm_pin_cfg_t *cfg)
Configure GTIOR for one PWM output pin.
@ k_ra8_gpt_stop_low
OnDFLT = 0 -> stop level low.
@ k_ra8_gpt_pin_a
GTIOCnA – compare register A path.
@ k_ra8_gpt_disable_none
POEG fault does not affect pin.
@ k_ra8_gpt_mode_saw_pwm
Saw-wave PWM (up-count).
@ k_ra8_gpt_pol_active_high
Output is high while duty < count.
ra8_err_t ra8_gpt_init(uint8_t channel, const ra8_gpt_cfg_t *cfg)
Initialise a GPT channel with a full config descriptor.
@ k_ra8_gpt_ps_div_1
PCLKD / 1.
I2C Bus Interface (IIC) controller driver – polling mode.
ra8_err_t ra8_i2c_write(uint8_t channel, uint8_t peripheral_7b, const uint8_t *data, uint32_t len, bool send_stop)
Polling write of len bytes to a 7-bit peripheral address.
ra8_err_t ra8_i2c_transfer(uint8_t channel, uint8_t peripheral_7b, const uint8_t *wr, uint32_t wr_len, uint8_t *rd, uint32_t rd_len)
Combined write-then-RESTART-then-read in one bus transaction.
@ k_ra8_pfs_dscr_high_speed_high
10b: High-speed high drive.
ra8_port_pin_t
Packed (port << 8) | pin pin identifier.
@ k_ra8_level_high
Drive or read 1.
@ k_ra8_level_low
Drive or read 0.
High-level GPIO helpers on top of the PORT + PFS register layer.
ra8_err_t ra8_pfs_set_drive_strength(ra8_port_pin_t pin, ra8_pfs_dscr_t dscr)
Set the output drive strength (PmnPFS.DSCR) of an already-routed pin.
ra8_err_t ra8_gpio_output_init(ra8_port_pin_t pin, ra8_level_t init_level)
Configure a pin as a digital output and drive it to an initial level.
ra8_err_t ra8_gpio_write(ra8_port_pin_t pin, ra8_level_t level)
Drive a previously-configured output to the given level.
ra8_err_t ra8_pfs_route_peripheral(ra8_port_pin_t pin, ra8_psel_t psel, const char *owner)
Route a pin to a non-IRQ peripheral function via PFS.PSEL.
SysTick-based tick counter, delay and timestamp helpers.
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Configuration descriptor for ra8_gpt_init.
Configuration descriptor for ra8_gpt_pwm_pin_configure.