ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_gpt.h
Go to the documentation of this file.
1
32
33#pragma once
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#include <stdint.h>
40
41#include "ra8_dma.h"
42#include "ra8_err.h"
43
44/* =============================================================================
45 * Types
46 * =============================================================================
47 */
48
60
73
91
101typedef enum : uint32_t {
102 k_ra8_gpt_status_none = 0x00000000UL,
103 k_ra8_gpt_status_ccra = 0x00000001UL,
104 k_ra8_gpt_status_ccrb = 0x00000002UL,
108
113typedef enum : uint8_t {
117
125typedef void (*ra8_gpt_event_fn_t)(void* ctx, uint32_t status_mask);
126
127/* =============================================================================
128 * PWM pin configuration (Sweep 3 Task 2 -- mirrors FSP r_gpt PWM pin API)
129 * =============================================================================
130 */
131
145typedef enum : uint8_t {
149
163
174
187
205
206/* =============================================================================
207 * Three-phase PWM (Sweep 3 Task 2 -- mirrors FSP r_gpt_three_phase)
208 * =============================================================================
209 */
210
221
247
248/* =============================================================================
249 * Lifecycle
250 * =============================================================================
251 */
252
268[[nodiscard]] ra8_err_t ra8_gpt_init(uint8_t channel, const ra8_gpt_cfg_t* cfg);
269
274[[nodiscard]] ra8_err_t ra8_gpt_deinit(uint8_t channel);
275
276/* =============================================================================
277 * Legacy polling API
278 * =============================================================================
279 */
280
293[[nodiscard]] ra8_err_t ra8_gpt_start_free_run(uint8_t channel, uint32_t period);
294
302[[nodiscard]] ra8_err_t ra8_gpt_stop(uint8_t channel);
303
312[[nodiscard]] ra8_err_t ra8_gpt_read(uint8_t channel, uint32_t* out);
313
314/* =============================================================================
315 * Runtime reconfigure
316 * =============================================================================
317 */
318
326[[nodiscard]] ra8_err_t ra8_gpt_set_period(uint8_t channel, uint32_t period);
327
336[[nodiscard]] ra8_err_t ra8_gpt_set_duty(uint8_t channel, ra8_gpt_ccr_sel_t which, uint32_t value);
337
338/* =============================================================================
339 * Sweep 3 Task 2 -- runtime PWM duty / period / counter / dead time
340 * =============================================================================
341 */
342
374[[nodiscard]] ra8_err_t ra8_gpt_period_set(uint8_t channel, uint32_t period_counts);
375
409[[nodiscard]] ra8_err_t
410ra8_gpt_duty_cycle_set(uint8_t channel, ra8_gpt_pwm_pin_t pin, uint32_t compare_counts);
411
439[[nodiscard]] ra8_err_t ra8_gpt_counter_set(uint8_t channel, uint32_t value);
440
474[[nodiscard]] ra8_err_t
476
506[[nodiscard]] ra8_err_t
507ra8_gpt_dead_time_set(uint8_t channel, uint32_t rising_dt, uint32_t falling_dt);
508
509/* =============================================================================
510 * Three-phase synchronized PWM (FSP r_gpt_three_phase mirror)
511 * =============================================================================
512 */
513
546
579[[nodiscard]] ra8_err_t
580ra8_gpt_three_phase_set_duty(uint32_t u_duty, uint32_t v_duty, uint32_t w_duty);
581
602[[nodiscard]] ra8_err_t ra8_gpt_three_phase_close(void);
603
604/* =============================================================================
605 * Status
606 * =============================================================================
607 */
608
616[[nodiscard]] ra8_err_t ra8_gpt_get_status(uint8_t channel, uint32_t* out_mask);
617
622[[nodiscard]] ra8_err_t ra8_gpt_clear_status(uint8_t channel, uint32_t mask);
623
624/* =============================================================================
625 * Interrupt path
626 * =============================================================================
627 */
628
637[[nodiscard]] ra8_err_t ra8_gpt_attach_handler(uint8_t channel, ra8_gpt_event_fn_t fn, void* ctx);
638
639/* =============================================================================
640 * Power transition
641 * =============================================================================
642 */
643
648[[nodiscard]] ra8_err_t ra8_gpt_enter_stop(uint8_t channel);
649
654[[nodiscard]] ra8_err_t ra8_gpt_exit_stop(uint8_t channel);
655
656/* =============================================================================
657 * DMA TX / RX
658 * =============================================================================
659 */
660
693[[nodiscard]] ra8_err_t ra8_gpt_write_dma(uint8_t channel,
694 const uint32_t* periods,
695 uint16_t count,
696 ra8_dma_complete_fn_t on_complete,
697 void* ctx,
698 uint8_t* out_dma_channel);
699
733[[nodiscard]] ra8_err_t ra8_gpt_read_dma(uint8_t channel,
734 uint32_t* out_counts,
735 uint16_t count,
736 ra8_dma_complete_fn_t on_complete,
737 void* ctx,
738 uint8_t* out_dma_channel);
739
740/* =============================================================================
741 * ISR dispatch
742 * =============================================================================
743 */
744
759void ra8_gpt_dispatch_ovf(uint8_t channel);
760
775void ra8_gpt_dispatch_und(uint8_t channel);
776
791void ra8_gpt_dispatch_ccra(uint8_t channel);
792
807void ra8_gpt_dispatch_ccrb(uint8_t channel);
808
809/*
810 * Input capture & external event counting live in ra8_gpt_capture.h, which
811 * includes THIS header for its base types. The include is one-directional
812 * (this header does NOT include it back) so there is no include cycle;
813 * consumers that need the capture / event-count API include ra8_gpt_capture.h.
814 */
815
816#ifdef __cplusplus
817}
818#endif
ra8_board_eth_pin_t pin
Pin.
Generic DMA transfer substrate (DMAC engine).
void(* ra8_dma_complete_fn_t)(void *ctx)
Caller-supplied completion callback.
Definition ra8_dma.h:88
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
void ra8_gpt_dispatch_ccrb(uint8_t channel)
Dispatch GPT compare-match B (GTCIB) – clear + fire callback.
Definition ra8_gpt.c:919
ra8_gpt_three_phase_idx_t
Index into ra8_gpt_three_phase_cfg_t::channels for U/V/W.
Definition ra8_gpt.h:215
@ k_ra8_gpt_three_phase_count
Number of phases.
Definition ra8_gpt.h:219
@ k_ra8_gpt_three_phase_w
W-phase channel slot.
Definition ra8_gpt.h:218
@ k_ra8_gpt_three_phase_v
V-phase channel slot.
Definition ra8_gpt.h:217
@ k_ra8_gpt_three_phase_u
U-phase channel slot.
Definition ra8_gpt.h:216
ra8_err_t ra8_gpt_pwm_pin_configure(uint8_t channel, ra8_gpt_pwm_pin_t pin, const ra8_gpt_pwm_pin_cfg_t *cfg)
Configure GTIOR for one PWM output pin.
Definition ra8_gpt.c:678
ra8_gpt_pwm_stop_level_t
Pin level when the timer is stopped.
Definition ra8_gpt.h:170
@ k_ra8_gpt_stop_low
OnDFLT = 0 -> stop level low.
Definition ra8_gpt.h:171
@ k_ra8_gpt_stop_high
OnDFLT = 1 -> stop level high.
Definition ra8_gpt.h:172
ra8_err_t ra8_gpt_dead_time_set(uint8_t channel, uint32_t rising_dt, uint32_t falling_dt)
Programme the dead-time value pair for complementary PWM.
Definition ra8_gpt.c:716
ra8_err_t ra8_gpt_start_free_run(uint8_t channel, uint32_t period)
Configure a GPT channel as a free-running up-counter.
Definition ra8_gpt.c:274
ra8_gpt_pwm_pin_t
Selector for the GTIOCnA / GTIOCnB PWM output pins.
Definition ra8_gpt.h:145
@ k_ra8_gpt_pin_b
GTIOCnB – compare register B path.
Definition ra8_gpt.h:147
@ k_ra8_gpt_pin_a
GTIOCnA – compare register A path.
Definition ra8_gpt.h:146
ra8_gpt_pwm_disable_t
Output-disable-on-POEG-fault behaviour (GTIOR.OADF / OBDF).
Definition ra8_gpt.h:181
@ k_ra8_gpt_disable_drive_low
POEG fault -> drive low.
Definition ra8_gpt.h:184
@ k_ra8_gpt_disable_drive_hi
POEG fault -> drive high.
Definition ra8_gpt.h:185
@ k_ra8_gpt_disable_high_z
POEG fault -> Hi-Z.
Definition ra8_gpt.h:183
@ k_ra8_gpt_disable_none
POEG fault does not affect pin.
Definition ra8_gpt.h:182
ra8_err_t ra8_gpt_stop(uint8_t channel)
Stop a GPT channel.
Definition ra8_gpt.c:303
ra8_err_t ra8_gpt_attach_handler(uint8_t channel, ra8_gpt_event_fn_t fn, void *ctx)
Attach a GPT event callback for a channel.
Definition ra8_gpt.c:429
ra8_gpt_ccr_sel_t
Selector for ra8_gpt_set_duty.
Definition ra8_gpt.h:113
@ k_ra8_gpt_ccr_a
GTCCRA.
Definition ra8_gpt.h:114
@ k_ra8_gpt_ccr_b
GTCCRB.
Definition ra8_gpt.h:115
ra8_err_t ra8_gpt_set_period(uint8_t channel, uint32_t period)
Change the GPT period (GTPR / GTPBR) at runtime.
Definition ra8_gpt.c:382
void ra8_gpt_dispatch_und(uint8_t channel)
Dispatch GPT underflow (GTCIU) – clear + fire callback.
Definition ra8_gpt.c:907
ra8_err_t ra8_gpt_set_duty(uint8_t channel, ra8_gpt_ccr_sel_t which, uint32_t value)
Change one compare register (GTCCRA / GTCCRB) at runtime.
Definition ra8_gpt.c:394
ra8_err_t ra8_gpt_write_dma(uint8_t channel, const uint32_t *periods, uint16_t count, ra8_dma_complete_fn_t on_complete, void *ctx, uint8_t *out_dma_channel)
Stream a buffer of period values into GPT GTPR via DMA.
Definition ra8_gpt.c:463
ra8_err_t ra8_gpt_three_phase_set_duty(uint32_t u_duty, uint32_t v_duty, uint32_t w_duty)
Atomically update U/V/W compare values via the shadow buffer.
Definition ra8_gpt.c:833
ra8_gpt_status_mask_t
Bit mask of GPT status flags (GTST register subset).
Definition ra8_gpt.h:101
@ k_ra8_gpt_status_none
RA8 GPT status none.
Definition ra8_gpt.h:102
@ k_ra8_gpt_status_ccrb
GTST.TCFB (bit 1).
Definition ra8_gpt.h:104
@ k_ra8_gpt_status_ccra
GTST.TCFA (bit 0).
Definition ra8_gpt.h:103
@ k_ra8_gpt_status_overflow
GTST.TCFPO (bit 6).
Definition ra8_gpt.h:105
@ k_ra8_gpt_status_underflow
GTST.TCFPU (bit 7).
Definition ra8_gpt.h:106
void(* ra8_gpt_event_fn_t)(void *ctx, uint32_t status_mask)
GPT IRQ event callback signature.
Definition ra8_gpt.h:125
ra8_err_t ra8_gpt_duty_cycle_set(uint8_t channel, ra8_gpt_pwm_pin_t pin, uint32_t compare_counts)
Update one PWM compare value via the shadow buffer.
Definition ra8_gpt.c:613
ra8_err_t ra8_gpt_read_dma(uint8_t channel, uint32_t *out_counts, uint16_t count, ra8_dma_complete_fn_t on_complete, void *ctx, uint8_t *out_dma_channel)
Capture a stream of GTCNT values into a buffer via DMA.
Definition ra8_gpt.c:493
ra8_gpt_mode_t
GPT counter-mode selection (GTCR.MD field).
Definition ra8_gpt.h:53
@ k_ra8_gpt_mode_triangle_pwm2
Triangle-wave PWM 1.
Definition ra8_gpt.h:57
@ k_ra8_gpt_mode_saw_one_shot
Saw-wave one-shot.
Definition ra8_gpt.h:55
@ k_ra8_gpt_mode_saw_pwm
Saw-wave PWM (up-count).
Definition ra8_gpt.h:54
@ k_ra8_gpt_mode_triangle_pwm3
Triangle-wave PWM 2.
Definition ra8_gpt.h:58
@ k_ra8_gpt_mode_triangle_pwm
Triangle-wave PWM symmetric.
Definition ra8_gpt.h:56
ra8_err_t ra8_gpt_clear_status(uint8_t channel, uint32_t mask)
Clear GTST flag bits (write-0 to clear).
Definition ra8_gpt.c:418
ra8_err_t ra8_gpt_exit_stop(uint8_t channel)
Exit MSTP-gated stop.
Definition ra8_gpt.c:453
ra8_err_t ra8_gpt_three_phase_close(void)
Stop and tear down the three U/V/W channels.
Definition ra8_gpt.c:860
ra8_err_t ra8_gpt_three_phase_open(const ra8_gpt_three_phase_cfg_t *cfg)
Open three GPT channels as a phase-synchronized U/V/W triple.
Definition ra8_gpt.c:799
ra8_gpt_pwm_polarity_t
Output polarity for ra8_gpt_pwm_pin_configure.
Definition ra8_gpt.h:159
@ k_ra8_gpt_pol_active_low
Output is low while duty < count.
Definition ra8_gpt.h:161
@ k_ra8_gpt_pol_active_high
Output is high while duty < count.
Definition ra8_gpt.h:160
void ra8_gpt_dispatch_ccra(uint8_t channel)
Dispatch GPT compare-match A (GTCIA) – clear + fire callback.
Definition ra8_gpt.c:913
void ra8_gpt_dispatch_ovf(uint8_t channel)
Dispatch GPT overflow (GTCIV) – clear + fire callback.
Definition ra8_gpt.c:901
ra8_err_t ra8_gpt_init(uint8_t channel, const ra8_gpt_cfg_t *cfg)
Initialise a GPT channel with a full config descriptor.
Definition ra8_gpt.c:329
ra8_err_t ra8_gpt_counter_set(uint8_t channel, uint32_t value)
Force GTCNT to value (timer must be stopped).
Definition ra8_gpt.c:637
ra8_err_t ra8_gpt_deinit(uint8_t channel)
Tear down a channel (stop + MSTP release).
Definition ra8_gpt.c:365
ra8_err_t ra8_gpt_get_status(uint8_t channel, uint32_t *out_mask)
Read GTST overflow / underflow / compare flags.
Definition ra8_gpt.c:408
ra8_err_t ra8_gpt_read(uint8_t channel, uint32_t *out)
Read the current counter value.
Definition ra8_gpt.c:314
ra8_err_t ra8_gpt_enter_stop(uint8_t channel)
Put a channel into MSTP-gated stop.
Definition ra8_gpt.c:439
ra8_gpt_prescaler_t
GTCR.TPCS clock prescaler.
Definition ra8_gpt.h:65
@ k_ra8_gpt_ps_div_256
PCLKD / 256.
Definition ra8_gpt.h:70
@ k_ra8_gpt_ps_div_1
PCLKD / 1.
Definition ra8_gpt.h:66
@ k_ra8_gpt_ps_div_4
PCLKD / 4.
Definition ra8_gpt.h:67
@ k_ra8_gpt_ps_div_1024
PCLKD / 1024.
Definition ra8_gpt.h:71
@ k_ra8_gpt_ps_div_64
PCLKD / 64.
Definition ra8_gpt.h:69
@ k_ra8_gpt_ps_div_16
PCLKD / 16.
Definition ra8_gpt.h:68
ra8_err_t ra8_gpt_period_set(uint8_t channel, uint32_t period_counts)
Update the GPT period via the shadow buffer (GTPBR).
Definition ra8_gpt.c:595
Configuration descriptor for ra8_gpt_init.
Definition ra8_gpt.h:83
ra8_gpt_prescaler_t prescaler
Clock divider.
Definition ra8_gpt.h:85
uint32_t duty_b
GTCCRB compare/duty (PWM B).
Definition ra8_gpt.h:88
bool auto_start
True -> start after init.
Definition ra8_gpt.h:89
ra8_gpt_mode_t mode
Counter mode.
Definition ra8_gpt.h:84
uint32_t duty_a
GTCCRA compare/duty (PWM A).
Definition ra8_gpt.h:87
uint32_t period
GTPR period.
Definition ra8_gpt.h:86
Configuration descriptor for ra8_gpt_pwm_pin_configure.
Definition ra8_gpt.h:199
ra8_gpt_pwm_polarity_t polarity
Active-high vs active-low.
Definition ra8_gpt.h:201
bool output_enable
OAE / OBE – enable pin.
Definition ra8_gpt.h:200
ra8_gpt_pwm_disable_t disable_on_fault
OADF / OBDF (POEG).
Definition ra8_gpt.h:203
ra8_gpt_pwm_stop_level_t stop_level
OADFLT / OBDFLT.
Definition ra8_gpt.h:202
Configuration descriptor for ra8_gpt_three_phase_open.
Definition ra8_gpt.h:238
ra8_gpt_mode_t mode
Triangle/saw.
Definition ra8_gpt.h:240
uint32_t initial_duty_u
Initial duty U.
Definition ra8_gpt.h:243
uint32_t period_counts
Shared GTPR.
Definition ra8_gpt.h:242
ra8_gpt_prescaler_t prescaler
Clock div.
Definition ra8_gpt.h:241
uint32_t initial_duty_w
Initial duty W.
Definition ra8_gpt.h:245
uint8_t channels[k_ra8_gpt_three_phase_count]
U/V/W ch ids.
Definition ra8_gpt.h:239
uint32_t initial_duty_v
Initial duty V.
Definition ra8_gpt.h:244