53typedef enum : uint8_t {
65typedef enum : uint8_t {
101typedef enum : uint32_t {
113typedef enum : uint8_t {
145typedef enum : uint8_t {
159typedef enum : uint8_t {
170typedef enum : uint8_t {
181typedef enum : uint8_t {
215typedef enum : uint8_t {
694 const uint32_t* periods,
698 uint8_t* out_dma_channel);
734 uint32_t* out_counts,
738 uint8_t* out_dma_channel);
ra8_board_eth_pin_t pin
Pin.
Generic DMA transfer substrate (DMAC engine).
void(* ra8_dma_complete_fn_t)(void *ctx)
Caller-supplied completion callback.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
void ra8_gpt_dispatch_ccrb(uint8_t channel)
Dispatch GPT compare-match B (GTCIB) – clear + fire callback.
ra8_gpt_three_phase_idx_t
Index into ra8_gpt_three_phase_cfg_t::channels for U/V/W.
@ k_ra8_gpt_three_phase_count
Number of phases.
@ k_ra8_gpt_three_phase_w
W-phase channel slot.
@ k_ra8_gpt_three_phase_v
V-phase channel slot.
@ k_ra8_gpt_three_phase_u
U-phase channel slot.
ra8_err_t ra8_gpt_pwm_pin_configure(uint8_t channel, ra8_gpt_pwm_pin_t pin, const ra8_gpt_pwm_pin_cfg_t *cfg)
Configure GTIOR for one PWM output pin.
ra8_gpt_pwm_stop_level_t
Pin level when the timer is stopped.
@ k_ra8_gpt_stop_low
OnDFLT = 0 -> stop level low.
@ k_ra8_gpt_stop_high
OnDFLT = 1 -> stop level high.
ra8_err_t ra8_gpt_dead_time_set(uint8_t channel, uint32_t rising_dt, uint32_t falling_dt)
Programme the dead-time value pair for complementary PWM.
ra8_err_t ra8_gpt_start_free_run(uint8_t channel, uint32_t period)
Configure a GPT channel as a free-running up-counter.
ra8_gpt_pwm_pin_t
Selector for the GTIOCnA / GTIOCnB PWM output pins.
@ k_ra8_gpt_pin_b
GTIOCnB – compare register B path.
@ k_ra8_gpt_pin_a
GTIOCnA – compare register A path.
ra8_gpt_pwm_disable_t
Output-disable-on-POEG-fault behaviour (GTIOR.OADF / OBDF).
@ k_ra8_gpt_disable_drive_low
POEG fault -> drive low.
@ k_ra8_gpt_disable_drive_hi
POEG fault -> drive high.
@ k_ra8_gpt_disable_high_z
POEG fault -> Hi-Z.
@ k_ra8_gpt_disable_none
POEG fault does not affect pin.
ra8_err_t ra8_gpt_stop(uint8_t channel)
Stop a GPT channel.
ra8_err_t ra8_gpt_attach_handler(uint8_t channel, ra8_gpt_event_fn_t fn, void *ctx)
Attach a GPT event callback for a channel.
ra8_gpt_ccr_sel_t
Selector for ra8_gpt_set_duty.
ra8_err_t ra8_gpt_set_period(uint8_t channel, uint32_t period)
Change the GPT period (GTPR / GTPBR) at runtime.
void ra8_gpt_dispatch_und(uint8_t channel)
Dispatch GPT underflow (GTCIU) – clear + fire callback.
ra8_err_t ra8_gpt_set_duty(uint8_t channel, ra8_gpt_ccr_sel_t which, uint32_t value)
Change one compare register (GTCCRA / GTCCRB) at runtime.
ra8_err_t ra8_gpt_write_dma(uint8_t channel, const uint32_t *periods, uint16_t count, ra8_dma_complete_fn_t on_complete, void *ctx, uint8_t *out_dma_channel)
Stream a buffer of period values into GPT GTPR via DMA.
ra8_err_t ra8_gpt_three_phase_set_duty(uint32_t u_duty, uint32_t v_duty, uint32_t w_duty)
Atomically update U/V/W compare values via the shadow buffer.
ra8_gpt_status_mask_t
Bit mask of GPT status flags (GTST register subset).
@ k_ra8_gpt_status_none
RA8 GPT status none.
@ k_ra8_gpt_status_ccrb
GTST.TCFB (bit 1).
@ k_ra8_gpt_status_ccra
GTST.TCFA (bit 0).
@ k_ra8_gpt_status_overflow
GTST.TCFPO (bit 6).
@ k_ra8_gpt_status_underflow
GTST.TCFPU (bit 7).
void(* ra8_gpt_event_fn_t)(void *ctx, uint32_t status_mask)
GPT IRQ event callback signature.
ra8_err_t ra8_gpt_duty_cycle_set(uint8_t channel, ra8_gpt_pwm_pin_t pin, uint32_t compare_counts)
Update one PWM compare value via the shadow buffer.
ra8_err_t ra8_gpt_read_dma(uint8_t channel, uint32_t *out_counts, uint16_t count, ra8_dma_complete_fn_t on_complete, void *ctx, uint8_t *out_dma_channel)
Capture a stream of GTCNT values into a buffer via DMA.
ra8_gpt_mode_t
GPT counter-mode selection (GTCR.MD field).
@ k_ra8_gpt_mode_triangle_pwm2
Triangle-wave PWM 1.
@ k_ra8_gpt_mode_saw_one_shot
Saw-wave one-shot.
@ k_ra8_gpt_mode_saw_pwm
Saw-wave PWM (up-count).
@ k_ra8_gpt_mode_triangle_pwm3
Triangle-wave PWM 2.
@ k_ra8_gpt_mode_triangle_pwm
Triangle-wave PWM symmetric.
ra8_err_t ra8_gpt_clear_status(uint8_t channel, uint32_t mask)
Clear GTST flag bits (write-0 to clear).
ra8_err_t ra8_gpt_exit_stop(uint8_t channel)
Exit MSTP-gated stop.
ra8_err_t ra8_gpt_three_phase_close(void)
Stop and tear down the three U/V/W channels.
ra8_err_t ra8_gpt_three_phase_open(const ra8_gpt_three_phase_cfg_t *cfg)
Open three GPT channels as a phase-synchronized U/V/W triple.
ra8_gpt_pwm_polarity_t
Output polarity for ra8_gpt_pwm_pin_configure.
@ k_ra8_gpt_pol_active_low
Output is low while duty < count.
@ k_ra8_gpt_pol_active_high
Output is high while duty < count.
void ra8_gpt_dispatch_ccra(uint8_t channel)
Dispatch GPT compare-match A (GTCIA) – clear + fire callback.
void ra8_gpt_dispatch_ovf(uint8_t channel)
Dispatch GPT overflow (GTCIV) – clear + fire callback.
ra8_err_t ra8_gpt_init(uint8_t channel, const ra8_gpt_cfg_t *cfg)
Initialise a GPT channel with a full config descriptor.
ra8_err_t ra8_gpt_counter_set(uint8_t channel, uint32_t value)
Force GTCNT to value (timer must be stopped).
ra8_err_t ra8_gpt_deinit(uint8_t channel)
Tear down a channel (stop + MSTP release).
ra8_err_t ra8_gpt_get_status(uint8_t channel, uint32_t *out_mask)
Read GTST overflow / underflow / compare flags.
ra8_err_t ra8_gpt_read(uint8_t channel, uint32_t *out)
Read the current counter value.
ra8_err_t ra8_gpt_enter_stop(uint8_t channel)
Put a channel into MSTP-gated stop.
ra8_gpt_prescaler_t
GTCR.TPCS clock prescaler.
@ k_ra8_gpt_ps_div_256
PCLKD / 256.
@ k_ra8_gpt_ps_div_1
PCLKD / 1.
@ k_ra8_gpt_ps_div_4
PCLKD / 4.
@ k_ra8_gpt_ps_div_1024
PCLKD / 1024.
@ k_ra8_gpt_ps_div_64
PCLKD / 64.
@ k_ra8_gpt_ps_div_16
PCLKD / 16.
ra8_err_t ra8_gpt_period_set(uint8_t channel, uint32_t period_counts)
Update the GPT period via the shadow buffer (GTPBR).
Configuration descriptor for ra8_gpt_init.
ra8_gpt_prescaler_t prescaler
Clock divider.
uint32_t duty_b
GTCCRB compare/duty (PWM B).
bool auto_start
True -> start after init.
ra8_gpt_mode_t mode
Counter mode.
uint32_t duty_a
GTCCRA compare/duty (PWM A).
uint32_t period
GTPR period.
Configuration descriptor for ra8_gpt_pwm_pin_configure.
ra8_gpt_pwm_polarity_t polarity
Active-high vs active-low.
bool output_enable
OAE / OBE – enable pin.
ra8_gpt_pwm_disable_t disable_on_fault
OADF / OBDF (POEG).
ra8_gpt_pwm_stop_level_t stop_level
OADFLT / OBDFLT.
Configuration descriptor for ra8_gpt_three_phase_open.
ra8_gpt_mode_t mode
Triangle/saw.
uint32_t initial_duty_u
Initial duty U.
uint32_t period_counts
Shared GTPR.
ra8_gpt_prescaler_t prescaler
Clock div.
uint32_t initial_duty_w
Initial duty W.
uint8_t channels[k_ra8_gpt_three_phase_count]
U/V/W ch ids.
uint32_t initial_duty_v
Initial duty V.