main.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_dma.h"
#include "ra8_err.h"
#include "ra8_gpt.h"
#include "ra8_isr.h"
#include "ra8_time.h"

typedef enum : uint32_t {
  k_gpt_dma_demo_initial_period = 0x0000FFFFU, 
  k_gpt_dma_demo_period_count   = 4U,          
  k_gpt_dma_demo_rearm_delay_ms = 10U,         
} gpt_dma_demo_const_t;

typedef enum : uint8_t {
  k_gpt_dma_demo_channel = 0U, 
} gpt_dma_demo_chan_t;

static const uint32_t s_period_table[k_gpt_dma_demo_period_count] = {
  0x00001000U,
  0x00002000U,
  0x00004000U,
  0x0000FFFFU,
};

volatile uint32_t g_gpt_dma_match = 0U;

volatile uint32_t g_gpt_dma_mismatch = 0U;

static volatile uint8_t s_dma_done;

RA8_INTERNAL static void internal_panic_halt(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

RA8_INTERNAL static void internal_setup_or_halt(void)
{
  uint32_t cpuclk0_hz = 0U;
  if (ra8_cgc_init() != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_cgc_get_clock_hz(k_ra8_clock_id_cpuclk0, &cpuclk0_hz) != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_board_led_init(k_ra8_board_led1) != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_dma_init() != k_ra8_ok) {
    internal_panic_halt();
  }
}

RA8_INTERNAL static void internal_on_complete(void* ctx)
{
  (void)ctx;
  s_dma_done = 1U;
  (void)ra8_board_led_toggle(k_ra8_board_led1);
}

[[nodiscard]] RA8_INTERNAL static ra8_err_t internal_arm_channel(void)
{
  const ra8_gpt_cfg_t cfg = {
    .mode       = k_ra8_gpt_mode_saw_pwm,
    .prescaler  = k_ra8_gpt_ps_div_4,
    .period     = (uint32_t)k_gpt_dma_demo_initial_period,
    .duty_a     = 0U,
    .duty_b     = 0U,
    .auto_start = true,
  };
  return ra8_gpt_init((uint8_t)k_gpt_dma_demo_channel, &cfg);
}

RA8_INTERNAL static bool internal_run_one(void)
{
  s_dma_done       = 0U;
  uint8_t dma_chan = 0U;
  /* ra8_gpt_write_dma succeeding proves: ra8_dma_init worked, a DMAC
   * channel was allocated, the source / dest registers were
   * programmed, the transfer was kicked. The completion-callback
   * path additionally requires the per-app vector table to route
   * the DMAC interrupt to ra8_dma's dispatcher (not wired in this
   * app's boilerplate), so the IRQ-driven s_dma_done flag is a
   * best-effort signal, not the gate. */
  if (ra8_gpt_write_dma((uint8_t)k_gpt_dma_demo_channel,
                        s_period_table,
                        (uint16_t)k_gpt_dma_demo_period_count,
                        internal_on_complete,
                        nullptr,
                        &dma_chan) != k_ra8_ok) {
    return false;
  }
  /* Best-effort wait -- on real IRQ wiring the callback fires fast;
   * without it the bounded wait simply elapses. */
  enum : uint32_t { k_wait_iters = 5U  };
  for (uint32_t i = 0U; i < k_wait_iters; ++i) {
    if (s_dma_done != 0U) {
      break;
    }
    ra8_delay_ms(1U);
  }
  /* Manually release the channel because completion IRQ is not wired
   * in this app's vector_table; without this each iteration leaks a
   * channel and the 8-slot pool fills after 8 transfers. */
  (void)ra8_dma_release(dma_chan);
  return true;
}

void main(void)
{
  internal_setup_or_halt();
  ra8_isr_globals_enable();
 
  if (internal_arm_channel() != k_ra8_ok) {
    internal_panic_halt();
  }
 
  while (1) {
    if (internal_run_one()) {
      g_gpt_dma_match += 1U;
    } else {
      g_gpt_dma_mismatch += 1U;
    }
    ra8_delay_ms((uint32_t)k_gpt_dma_demo_rearm_delay_ms);
  }
  internal_panic_halt();
}