ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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main.c
Go to the documentation of this file.
1
29
30#include <stdint.h>
31
32#include "ra8_attributes.h"
33#include "ra8_board_ek_ra8d2.h"
34#include "ra8_boot_entry.h"
35#include "ra8_cgc.h"
36#include "ra8_elc.h"
37#include "ra8_err.h"
38#include "ra8_gpt.h"
39#include "ra8_isr.h"
40#include "ra8_time.h"
41
48
50typedef enum : uint16_t {
54
68volatile uint32_t g_gpt_irq_count = 0U;
69
82{
83 while (1) {
84 __asm__ volatile("wfi");
85 }
86}
87
109{
110 (void)ctx;
111 g_gpt_irq_count += 1U;
113}
114
127{
128 uint32_t cpuclk0_hz = 0U;
129 if (ra8_cgc_init() != k_ra8_ok) {
131 }
134 }
135 if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
137 }
140 }
141}
142
155{
156 ra8_err_t err = ra8_isr_init();
157 if (err != k_ra8_ok) {
158 return err;
159 }
162 nullptr,
164 nullptr);
165 if (err != k_ra8_ok) {
166 return err;
167 }
168 const ra8_gpt_cfg_t cfg = {
170 .prescaler = k_ra8_gpt_ps_div_1,
171 .period = (uint32_t)k_gpt_irq_demo_period,
172 .duty_a = 0U,
173 .duty_b = 0U,
174 .auto_start = false,
175 };
176 err = ra8_gpt_init((uint8_t)k_gpt_irq_demo_channel, &cfg);
177 if (err != k_ra8_ok) {
178 return err;
179 }
181}
182
183void main(void)
184{
186
189 }
190
192
193 while (1) {
194 /* All observable work happens in internal_gpt_irq_demo_isr; the loop only idles. */
196 }
197
199}
void main(void)
Secure fallback main entry point.
Definition main.c:37
volatile uint32_t g_gpt_irq_count
Count of GPT0 overflow interrupts actually serviced by the ISR.
Definition main.c:68
gpt_irq_demo_const_t
Demo tunables.
Definition main.c:43
@ k_gpt_irq_demo_period
16-bit period at div_1.
Definition main.c:44
@ k_gpt_irq_demo_priority
NVIC priority for the overflow.
Definition main.c:46
@ k_gpt_irq_demo_loop_ms
Idle sleep between iterations.
Definition main.c:45
gpt_irq_demo_event_t
GPT channel and its counter-overflow ELC event (FSP ra8d2 0x0C1).
Definition main.c:50
@ k_gpt_irq_demo_channel
GPT IRQ demo channel.
Definition main.c:51
@ k_gpt_irq_demo_ovf_event
GPT0 GTCIV counter-overflow event.
Definition main.c:52
static void internal_gpt_irq_demo_panic_halt(void)
Park the processor after an unrecoverable demo failure.
Definition main.c:81
static void internal_gpt_irq_demo_isr(void *ctx)
GPT0 counter-overflow interrupt service routine.
Definition main.c:108
static void internal_gpt_irq_demo_setup_or_halt(void)
Initialize the clocks, timebase, and observable LED fixture.
Definition main.c:126
static ra8_err_t internal_gpt_irq_demo_arm(void)
Link the GPT0 overflow event to the NVIC and arm GPT0.
Definition main.c:154
Annotation-attribute framework macros for ra8-firmware.
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
ra8_err_t ra8_board_led_toggle(ra8_board_led_id_t led)
Toggle led's output state.
ra8_err_t ra8_board_led_init(ra8_board_led_id_t led)
Configure led as a digital output, initial level low (off).
@ k_ra8_board_led1
LED1, BLUE, P600 (jumper E27).
Boot entry points shared between a vector table and its startup code.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
Definition ra8_cgc.c:132
@ k_ra8_clock_id_cpuclk0
Cortex-M85 CPUCLK0.
Definition ra8_cgc.h:70
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Definition ra8_cgc.c:727
Event Link Controller driver.
ra8_elc_event_t
Partial list of ELC events (populate as drivers need them).
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
Full-featured General PWM Timer (GPT) driver.
ra8_err_t ra8_gpt_start_free_run(uint8_t channel, uint32_t period)
Configure a GPT channel as a free-running up-counter.
Definition ra8_gpt.c:274
@ k_ra8_gpt_mode_saw_pwm
Saw-wave PWM (up-count).
Definition ra8_gpt.h:54
ra8_err_t ra8_gpt_init(uint8_t channel, const ra8_gpt_cfg_t *cfg)
Initialise a GPT channel with a full config descriptor.
Definition ra8_gpt.c:329
@ k_ra8_gpt_ps_div_1
PCLKD / 1.
Definition ra8_gpt.h:66
NVIC + ICU IELSR allocator.
ra8_err_t ra8_isr_init(void)
Initialise the ra8_isr table.
Definition ra8_isr.c:229
void ra8_isr_globals_enable(void)
Globally enable maskable interrupts (PRIMASK = 0).
Definition ra8_isr.c:439
ra8_err_t ra8_isr_register(ra8_elc_event_t event, ra8_isr_handler_t handler, void *ctx, uint8_t priority, uint16_t *out_slot)
Allocate an IELSR slot for an ELC event + handler.
Definition ra8_isr.c:296
SysTick-based tick counter, delay and timestamp helpers.
ra8_err_t ra8_time_init(uint32_t cpu_hz)
Initialise SysTick for a 1 kHz tick interrupt.
Definition ra8_time.c:59
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Definition ra8_time.c:129
Configuration descriptor for ra8_gpt_init.
Definition ra8_gpt.h:83