GPT0 overflow interrupt -> NVIC -> ISR demo for EK-RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_elc.h"
#include "ra8_err.h"
#include "ra8_gpt.h"
#include "ra8_isr.h"
#include "ra8_time.h"

Include dependency graph for main.c:

Enumerations
enum	gpt_irq_demo_const_t : uint32_t { k_gpt_irq_demo_period = 0x0000FFFFU , k_gpt_irq_demo_loop_ms = 100U , k_gpt_irq_demo_priority = 3U }
	Demo tunables. More...
enum	gpt_irq_demo_event_t : uint16_t { k_gpt_irq_demo_channel = 0U , k_gpt_irq_demo_ovf_event = 0x0C1U }
	GPT channel and its counter-overflow ELC event (FSP ra8d2 0x0C1). More...

Functions
static void	internal_gpt_irq_demo_panic_halt (void)
	Park the processor after an unrecoverable demo failure.
static void	internal_gpt_irq_demo_isr (void *ctx)
	GPT0 counter-overflow interrupt service routine.
static void	internal_gpt_irq_demo_setup_or_halt (void)
	Initialize the clocks, timebase, and observable LED fixture.
static ra8_err_t	internal_gpt_irq_demo_arm (void)
	Link the GPT0 overflow event to the NVIC and arm GPT0.
void	main (void)
	The application entry point Reset_Handler hands control to.

Variables
volatile uint32_t	g_gpt_irq_count = 0U
	Count of GPT0 overflow interrupts actually serviced by the ISR.

Detailed Description

GPT0 overflow interrupt -> NVIC -> ISR demo for EK-RA8D2.

Tag: [Ring 6 / APP] {World: S}

Proves the full real interrupt path – a peripheral event linked through the ICU IELSR table, pended on the NVIC, and taken as a Cortex-M exception that runs an application ISR. Unlike the poll-based timer demos (agt_periodic, gpt_one_shot_demo), this app does NOT poll a status flag: it registers a handler for the GPT0 counter-overflow event with ra8_isr_register (which writes IELSR and enables the NVIC line), starts GPT0 in saw-wave PWM mode, and then sleeps. Every overflow fires internal_gpt_irq_demo_isr in handler mode, which increments g_gpt_irq_count and toggles board LED1. The main loop itself never touches the LED, so any LED transition is proof the real ISR ran.

Sequence:

CGC + SysTick + LED1 bring-up (panic-halt on any error).
ra8_isr_init then ra8_isr_register(GPT0 overflow, isr).
ra8_gpt_init (saw PWM) + ra8_gpt_start_free_run.
Loop: ra8_delay_ms – all work happens in the ISR.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file main.c.

Enumeration Type Documentation

◆ gpt_irq_demo_const_t

enum gpt_irq_demo_const_t : uint32_t

Demo tunables.

Enumerator
k_gpt_irq_demo_period	16-bit period at div_1.
k_gpt_irq_demo_loop_ms	Idle sleep between iterations.
k_gpt_irq_demo_priority	NVIC priority for the overflow.

Definition at line 43 of file main.c.

◆ gpt_irq_demo_event_t

enum gpt_irq_demo_event_t : uint16_t

GPT channel and its counter-overflow ELC event (FSP ra8d2 0x0C1).

Enumerator
k_gpt_irq_demo_channel	GPT IRQ demo channel.
k_gpt_irq_demo_ovf_event	GPT0 GTCIV counter-overflow event.

Definition at line 50 of file main.c.

Function Documentation

◆ internal_gpt_irq_demo_arm()

ra8_err_t internal_gpt_irq_demo_arm ( void )

staticnodiscard

Link the GPT0 overflow event to the NVIC and arm GPT0.

Returns: k_ra8_ok on success, else the first failing step's error.

Precondition: internal_gpt_irq_demo_setup_or_halt has run; interrupts not yet enabled.

Postcondition: On k_ra8_ok GPT0 is counting and its overflow vectors to the ISR.

Note: Not thread-safe (single-threaded boot context).

Since: 0.1.0

Definition at line 154 of file main.c.

References internal_gpt_irq_demo_isr(), k_gpt_irq_demo_channel, k_gpt_irq_demo_ovf_event, k_gpt_irq_demo_period, k_gpt_irq_demo_priority, k_ra8_gpt_mode_saw_pwm, k_ra8_gpt_ps_div_1, k_ra8_ok, ra8_gpt_init(), ra8_gpt_start_free_run(), RA8_INTERNAL, ra8_isr_init(), and ra8_isr_register().

Referenced by main().

◆ internal_gpt_irq_demo_isr()

void internal_gpt_irq_demo_isr ( void * ctx )

static

GPT0 counter-overflow interrupt service routine.

Runs in NVIC handler mode, reached via the real path: GPT0 overflow -> IELSR event link -> NVIC pend -> vector 16 + IRQ -> ra8_isr_dispatch -> here. Bumps the liveness counter and toggles LED1 so the effect is observable both on hardware (LED + memprobe) and in the emulator (LED transition + IRQ count).

Parameters

[in] ctx Unused registration context.

Returns: Nothing.

Precondition: Registered for the GPT0 overflow event via ra8_isr_register.; ctx is the unused registration context supplied by this application.

Postcondition: g_gpt_irq_count has advanced by one and LED1 has toggled.; No GPT configuration or interrupt routing is modified.

Note: Not re-entrant; a single GPT channel drives it.

Since: 0.1.0

Definition at line 108 of file main.c.

References g_gpt_irq_count, k_ra8_board_led1, ra8_board_led_toggle(), and RA8_INTERNAL.

Referenced by internal_gpt_irq_demo_arm().

◆ internal_gpt_irq_demo_panic_halt()

void internal_gpt_irq_demo_panic_halt ( void )

static

Park the processor after an unrecoverable demo failure.

Enters a permanent wait-for-interrupt loop so the failing state and liveness counter remain available to a debugger or HIL probe.

Precondition: Reset startup initialized the stack and exception environment.; The caller has determined that normal demo execution cannot continue.

Postcondition: Control never returns to the caller.; No further application-level state transition is attempted.

Note: An interrupt can wake one iteration, but the terminal loop resumes.

Since: 0.1.0

Definition at line 81 of file main.c.

References RA8_INTERNAL.

Referenced by internal_gpt_irq_demo_setup_or_halt(), and main().

◆ internal_gpt_irq_demo_setup_or_halt()

void internal_gpt_irq_demo_setup_or_halt ( void )

static

Initialize the clocks, timebase, and observable LED fixture.

Brings dependencies up in order and treats any failure as terminal, leaving interrupt routing disabled until the separate arm step.

Precondition: Reset startup completed data and BSS initialization.; Board clock and GPIO registers are in their reset-compatible state.

Postcondition: On return the CPU clock rate is known, the timebase runs, and LED1 is initialized.; Any failed prerequisite has entered the terminal panic loop.

Note: Single-shot boot helper; it is not reentrant.

Since: 0.1.0

Definition at line 126 of file main.c.

References internal_gpt_irq_demo_panic_halt(), k_ra8_board_led1, k_ra8_clock_id_cpuclk0, k_ra8_ok, ra8_board_led_init(), ra8_cgc_get_clock_hz(), ra8_cgc_init(), RA8_INTERNAL, and ra8_time_init().

Referenced by main().

◆ main()

void main ( void )

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has configured the clock tree and VTOR.

Postcondition: Control does not return; the image runs until reset or halt.; Any value the application wanted to report has been logged, not returned.

Note: Not thread-safe; single-threaded startup context only.

Warning: Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.

See also: SystemInit()

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the playback loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the sweep loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.

Postcondition: On clean entry the kernel runs the worker thread once.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the kernel runs the worker thread forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition: Reset_Handler has copied .data + zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: CPUCLK0 is raised to the PLL1 target before the kernel starts.; On clean entry the SD card thread runs forever.; On any HAL init failure the function halts in __WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the iso-IN feed loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition: Boot init has completed.; The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).

Postcondition: Diagnostic counter latched, CPU parked in a halt loop.; Function never returns.

Note: Single-threaded entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.; On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.; On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.

Postcondition: The shelf scans on the panel; taps open books, browse, and read.

Since: 0.1.0

Definition at line 183 of file main.c.

References internal_gpt_irq_demo_arm(), internal_gpt_irq_demo_panic_halt(), internal_gpt_irq_demo_setup_or_halt(), k_gpt_irq_demo_loop_ms, k_ra8_ok, ra8_delay_ms(), and ra8_isr_globals_enable().

Variable Documentation

◆ g_gpt_irq_count

volatile uint32_t g_gpt_irq_count = 0U

Count of GPT0 overflow interrupts actually serviced by the ISR.

Incremented only inside internal_gpt_irq_demo_isr. If the ICU event link, the NVIC enable, or the vector dispatch were broken this would never advance – so a non-zero value is direct evidence the real NVIC interrupt path ran. Read externally by J-Link (HIL) and by tools/ra8_emulator (emulator).

Note: Read externally only; the firmware main loop never reads it back.

Since: 0.1.0

Definition at line 68 of file main.c.

Referenced by internal_gpt_irq_demo_isr().

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ gpt_irq_demo_const_t

◆ gpt_irq_demo_event_t

Function Documentation

◆ internal_gpt_irq_demo_arm()

◆ internal_gpt_irq_demo_isr()

◆ internal_gpt_irq_demo_panic_halt()

◆ internal_gpt_irq_demo_setup_or_halt()

◆ main()

Variable Documentation

◆ g_gpt_irq_count