main.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_gpt.h"
#include "ra8_isr.h"
#include "ra8_time.h"

typedef enum : uint32_t {
  k_gpt_pwm_demo_period   = 0x0000FFFFU, 
  k_gpt_pwm_demo_step_ms  = 20U,         
  k_gpt_pwm_demo_step_pct = 1024U,       
} gpt_pwm_demo_const_t;

typedef enum : uint8_t {
  k_gpt_pwm_demo_channel = 0U, 
} gpt_pwm_demo_chan_t;

volatile uint32_t g_gpt_pwm_match = 0U;

volatile uint32_t g_gpt_pwm_mismatch = 0U;

RA8_INTERNAL static void internal_gpt_pwm_demo_panic_halt(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

RA8_INTERNAL static void internal_gpt_pwm_demo_setup_or_halt(void)
{
  uint32_t cpuclk0_hz = 0U;
  if (ra8_cgc_init() != k_ra8_ok) {
    internal_gpt_pwm_demo_panic_halt();
  }
  if (ra8_cgc_get_clock_hz(k_ra8_clock_id_cpuclk0, &cpuclk0_hz) != k_ra8_ok) {
    internal_gpt_pwm_demo_panic_halt();
  }
  if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
    internal_gpt_pwm_demo_panic_halt();
  }
  if (ra8_board_led_init(k_ra8_board_led1) != k_ra8_ok) {
    internal_gpt_pwm_demo_panic_halt();
  }
}

[[nodiscard]] RA8_INTERNAL static ra8_err_t internal_gpt_pwm_demo_arm(void)
{
  const ra8_gpt_cfg_t cfg = {
    .mode       = k_ra8_gpt_mode_saw_pwm,
    .prescaler  = k_ra8_gpt_ps_div_4,
    .period     = (uint32_t)k_gpt_pwm_demo_period,
    .duty_a     = (uint32_t)0U,
    .duty_b     = (uint32_t)0U,
    .auto_start = true,
  };
  return ra8_gpt_init((uint8_t)k_gpt_pwm_demo_channel, &cfg);
}
 
void main(void)
{
  internal_gpt_pwm_demo_setup_or_halt();
  ra8_isr_globals_enable();
 
  if (internal_gpt_pwm_demo_arm() != k_ra8_ok) {
    internal_gpt_pwm_demo_panic_halt();
  }
 
  uint32_t duty       = 0U;
  bool     up         = true;
  uint32_t prev_count = 0U;
  bool     have_prev  = false;
  while (1) {
    if (ra8_gpt_set_duty((uint8_t)k_gpt_pwm_demo_channel, k_ra8_gpt_ccr_a, duty) != k_ra8_ok) {
      g_gpt_pwm_mismatch += 1U;
      break;
    }
    uint32_t now_count = 0U;
    if (ra8_gpt_read((uint8_t)k_gpt_pwm_demo_channel, &now_count) != k_ra8_ok) {
      g_gpt_pwm_mismatch += 1U;
    } else if (have_prev && (now_count == prev_count)) {
      /* 20 ms passed but GTCNT did not move -- timer is wedged. */
      g_gpt_pwm_mismatch += 1U;
      prev_count = now_count;
    } else {
      g_gpt_pwm_match += 1U;
      prev_count = now_count;
      have_prev  = true;
    }
    if (up) {
      if (duty + (uint32_t)k_gpt_pwm_demo_step_pct >= (uint32_t)k_gpt_pwm_demo_period) {
        duty = (uint32_t)k_gpt_pwm_demo_period;
        up   = false;
      } else {
        duty += (uint32_t)k_gpt_pwm_demo_step_pct;
      }
    } else {
      if (duty <= (uint32_t)k_gpt_pwm_demo_step_pct) {
        duty = 0U;
        up   = true;
      } else {
        duty -= (uint32_t)k_gpt_pwm_demo_step_pct;
      }
    }
    ra8_delay_ms((uint32_t)k_gpt_pwm_demo_step_ms);
  }
  internal_gpt_pwm_demo_panic_halt();
}