main.c

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#include <stdint.h>
 
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_gpio_constants.h"
#include "ra8_gpt.h"
#include "ra8_gpt_capture.h"
#include "ra8_isr.h"
#include "ra8_mstp.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_time.h"

typedef enum : uint32_t {
  k_gpt_ecc_period          = 0xFFFFFFFFUL, 
  k_gpt_ecc_min_valid_ticks = 0x00000064UL, 
  k_gpt_ecc_max_valid_ticks = 0x7FFFFFFFUL, 
} gpt_ecc_period_const_t;

typedef enum : uint16_t {
  k_gpt_ecc_poll_period_ms = 5U, 
} gpt_ecc_poll_const_t;

typedef enum : uint8_t {
  k_gpt_ecc_capture_channel = 0U, 
  k_gpt_ecc_count_channel   = 1U, 
} gpt_ecc_layout_t;

static const ra8_port_pin_t k_gpt_ecc_pin_capture = RA8_PIN(k_ra8_port_4, k_ra8_pin_8);

static const ra8_port_pin_t k_gpt_ecc_pin_count = RA8_PIN(k_ra8_port_4, k_ra8_pin_9);

volatile uint32_t g_gpt_ecc_last_period = 0U;

volatile uint32_t g_gpt_ecc_capture_events = 0U;

volatile uint32_t g_gpt_ecc_pulse_count = 0U;

volatile uint32_t g_gpt_ecc_tick = 0U;

static void gpt_ecc_panic_halt(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

static bool gpt_ecc_period_valid(uint32_t delta_ticks)
{
  return (delta_ticks >= (uint32_t)k_gpt_ecc_min_valid_ticks) &&
         (delta_ticks <= (uint32_t)k_gpt_ecc_max_valid_ticks);
}

static void gpt_ecc_clocks_or_halt(void)
{
  uint32_t cpuclk0_hz = 0U;
  if (ra8_cgc_init() != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
  if (ra8_cgc_get_clock_hz(k_ra8_clock_id_cpuclk0, &cpuclk0_hz) != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
  if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
  if (ra8_board_led_init(k_ra8_board_led1) != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
  if (ra8_mstp_init() != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
}

static void gpt_ecc_route_pins_or_halt(void)
{
  if (ra8_pfs_route_peripheral(k_gpt_ecc_pin_capture, k_ra8_psel_gpt0, "gpt_ecc.gtioc0a") !=
      k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
  if (ra8_pfs_route_peripheral(k_gpt_ecc_pin_count, k_ra8_psel_gpt0, "gpt_ecc.gtioc1a") !=
      k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
}

static void gpt_ecc_timers_or_halt(void)
{
  const ra8_gpt_cfg_t cfg = {
    .mode       = k_ra8_gpt_mode_saw_pwm,
    .prescaler  = k_ra8_gpt_ps_div_1,
    .period     = (uint32_t)k_gpt_ecc_period,
    .duty_a     = 0U,
    .duty_b     = 0U,
    .auto_start = true,
  };
  if (ra8_gpt_init((uint8_t)k_gpt_ecc_capture_channel, &cfg) != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
  /* #185 input capture: latch GTCNT into GTCCRA on each GTIOC0A rising edge. */
  if (ra8_gpt_capture_configure((uint8_t)k_gpt_ecc_capture_channel,
                                k_ra8_gpt_ccr_a,
                                (uint32_t)k_ra8_gpt_cap_src_ioca_rising) != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
  if (ra8_gpt_init((uint8_t)k_gpt_ecc_count_channel, &cfg) != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
  /* #186 pulse counting: GTCNT counts GTIOC1A rising edges (up source only).
   * Quadrature variant: pass k_ra8_gpt_cnt_src_ioca_falling as the down
   * source instead of k_ra8_gpt_cnt_src_none for an encoder up/down count. */
  if (ra8_gpt_event_count_configure((uint8_t)k_gpt_ecc_count_channel,
                                    (uint32_t)k_ra8_gpt_cnt_src_ioca_rising,
                                    (uint32_t)k_ra8_gpt_cnt_src_none) != k_ra8_ok) {
    gpt_ecc_panic_halt();
  }
}

static bool gpt_ecc_service_capture(uint32_t* prev_latch)
{
  uint32_t status = 0U;
  if (ra8_gpt_get_status((uint8_t)k_gpt_ecc_capture_channel, &status) != k_ra8_ok) {
    return false;
  }
  if ((status & (uint32_t)k_ra8_gpt_status_ccra) == 0U) {
    return false;
  }
  uint32_t latch = 0U;
  if (ra8_gpt_capture_read((uint8_t)k_gpt_ecc_capture_channel, k_ra8_gpt_ccr_a, &latch) ==
      k_ra8_ok) {
    const uint32_t delta = latch - *prev_latch;
    *prev_latch          = latch;
    if (gpt_ecc_period_valid(delta)) {
      g_gpt_ecc_last_period    = delta;
      g_gpt_ecc_capture_events = g_gpt_ecc_capture_events + 1U;
      (void)ra8_board_led_toggle(k_ra8_board_led1);
    }
  }
  (void)ra8_gpt_clear_status((uint8_t)k_gpt_ecc_capture_channel, (uint32_t)k_ra8_gpt_status_ccra);
  return true;
}
 
void main(void)
{
  gpt_ecc_clocks_or_halt();
  gpt_ecc_route_pins_or_halt();
  gpt_ecc_timers_or_halt();
  ra8_isr_globals_enable();
 
  uint32_t prev_latch = 0U;
  uint32_t prev_free  = 0U;
  bool     have_prev  = false;
 
  while (1) {
    /* #185 input capture: hardware edge timestamp -> period. */
    (void)gpt_ecc_service_capture(&prev_latch);
 
    /* #186 external event counting: accumulated GTIOC1A edge count. */
    uint32_t pulses = 0U;
    if (ra8_gpt_read((uint8_t)k_gpt_ecc_count_channel, &pulses) == k_ra8_ok) {
      g_gpt_ecc_pulse_count = pulses;
    }
 
    /* Pin-independent liveness: capture-channel free-run counter alive. */
    uint32_t now_free = 0U;
    if (ra8_gpt_read((uint8_t)k_gpt_ecc_capture_channel, &now_free) == k_ra8_ok) {
      if (have_prev) {
        if (now_free != prev_free) {
          g_gpt_ecc_tick = g_gpt_ecc_tick + 1U;
        }
      }
      prev_free = now_free;
      have_prev = true;
    }
    ra8_delay_ms((uint32_t)k_gpt_ecc_poll_period_ms);
  }
  gpt_ecc_panic_halt();
}