GPT hardware input-capture + external event/pulse counting demo. More...

#include <stdint.h>
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_gpio_constants.h"
#include "ra8_gpt.h"
#include "ra8_gpt_capture.h"
#include "ra8_isr.h"
#include "ra8_mstp.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_time.h"

Include dependency graph for main.c:

Enumerations
enum	gpt_ecc_period_const_t : uint32_t { k_gpt_ecc_period = 0xFFFFFFFFUL , k_gpt_ecc_min_valid_ticks = 0x00000064UL , k_gpt_ecc_max_valid_ticks = 0x7FFFFFFFUL }
	32-bit counter tunables (free-run period + capture window). More...
enum	gpt_ecc_poll_const_t : uint16_t { k_gpt_ecc_poll_period_ms = 5U }
	Main-loop poll cadence in milliseconds. More...
enum	gpt_ecc_layout_t : uint8_t { k_gpt_ecc_capture_channel = 0U , k_gpt_ecc_count_channel = 1U }
	GPT channel + LED selection for the demo. More...

Functions
static void	gpt_ecc_panic_halt (void)
	Park the CPU after a fatal init failure.
static bool	gpt_ecc_period_valid (uint32_t delta_ticks)
	Classify a captured delta as a genuine signal period.
static void	gpt_ecc_clocks_or_halt (void)
	Bring up the core clocks, SysTick, and LED1.
static void	gpt_ecc_route_pins_or_halt (void)
	Route the two GTIOCnA edge-input pins to the GPT peripheral.
static void	gpt_ecc_timers_or_halt (void)
	Configure the capture (GPT0) and count (GPT1) timer channels.
static bool	gpt_ecc_service_capture (uint32_t *prev_latch)
	Service one input-capture poll: latch delta -> globals.
void	main (void)
	The application entry point Reset_Handler hands control to.

Variables
static const ra8_port_pin_t	k_gpt_ecc_pin_capture = ((ra8_port_pin_t)(((uint16_t)(k_ra8_port_4) << 8) \| (uint16_t)(k_ra8_pin_8)))
	GTIOC0A input pad for the capture channel (placeholder).
static const ra8_port_pin_t	k_gpt_ecc_pin_count = ((ra8_port_pin_t)(((uint16_t)(k_ra8_port_4) << 8) \| (uint16_t)(k_ra8_pin_9)))
	GTIOC1A input pad for the event-count channel (placeholder).
volatile uint32_t	g_gpt_ecc_last_period = 0U
	Most recent valid input-capture delta, in GPT counter ticks.
volatile uint32_t	g_gpt_ecc_capture_events = 0U
	Count of valid input-capture edges observed so far.
volatile uint32_t	g_gpt_ecc_pulse_count = 0U
	Latest accumulated external pulse count (GPT1 GTCNT).
volatile uint32_t	g_gpt_ecc_tick = 0U
	Pin-independent liveness counter.

Detailed Description

GPT hardware input-capture + external event/pulse counting demo.

Tag: [Ring 6 / APP] {World: S}

Demonstrates the two GPT edge-driven driver features that gpt_capture_input only approximates in software:

Input capture (issue #185): GPT0 runs as a free-running 32-bit up-counter. ra8_gpt_capture_configure arms GTICASR so that each rising edge on the GTIOC0A pin latches the live GTCNT value into GTCCRA (hardware timestamp – no CPU jitter). The loop polls the GTST.TCFA capture flag, reads the latch with ra8_gpt_capture_read, and the delta between two consecutive latches is the measured signal period in counter ticks.
External event / pulse counting (issue #186): GPT1 is switched out of internal-clock counting by ra8_gpt_event_count_configure (GTUPSR = GTIOC1A rising). GTCNT then increments once per external rising edge, so ra8_gpt_read returns an accumulated pulse count. The commented quadrature variant (up = GTIOC1A rising, down = GTIOC1A falling) turns the same channel into an encoder up/down counter.

The measured values are published in J-Link-readable globals so a future bench run can assert them against a known stimulus frequency.

Required hardware (why this is hw_pending):

The capture / count inputs need a real edge source. Either:

an external square-wave signal generator on the GTIOC0A and GTIOC1A pads, or
a jumper loop-back from a GPT PWM output pin (e.g. run gpt_pwm_demo on another channel and wire its GTIOCnA output to these capture inputs), or
a quadrature encoder for the up/down variant. The stock EK-RA8D2 also has no cleanly-broken-out GTIOCnA pad (the candidate pins collide with the debug UART per the Hardware User's Manual pin tables); see the TODO on the pin table below. Until a carrier board or jumper wiring exists this app is not bench-validated.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file main.c.

Enumeration Type Documentation

◆ gpt_ecc_layout_t

enum gpt_ecc_layout_t : uint8_t

GPT channel + LED selection for the demo.

Enumerator
k_gpt_ecc_capture_channel	GPT0: input-capture channel.
k_gpt_ecc_count_channel	GPT1: event-count channel.

Definition at line 94 of file main.c.

◆ gpt_ecc_period_const_t

enum gpt_ecc_period_const_t : uint32_t

32-bit counter tunables (free-run period + capture window).

k_gpt_ecc_period is the full-scale GTPR so GTCNT behaves as a 32-bit free-running accumulator. A captured delta is treated as a genuine signal period only when it falls inside

lower bound rejects sub-microsecond noise / contact bounce, the upper bound rejects the first (uninitialised) latch and any counter-wrap artefact.

Enumerator
k_gpt_ecc_period	GTPR full-scale.
k_gpt_ecc_min_valid_ticks	100: glitch-reject floor.
k_gpt_ecc_max_valid_ticks	Wrap / stale-latch ceiling.

Definition at line 76 of file main.c.

◆ gpt_ecc_poll_const_t

enum gpt_ecc_poll_const_t : uint16_t

Main-loop poll cadence in milliseconds.

Enumerator
k_gpt_ecc_poll_period_ms	Sample GTST / GTCNT every 5 ms.

Definition at line 86 of file main.c.

Function Documentation

◆ gpt_ecc_clocks_or_halt()

void gpt_ecc_clocks_or_halt ( void )

static

Bring up the core clocks, SysTick, and LED1.

CGC -> SysTick (from CPUCLK0) -> LED1 -> module-stop model. Any failure halts via gpt_ecc_panic_halt.

Precondition: Reset boot code has run (SystemInit set VTOR / FPU).; Called once from main before timer setup.

Postcondition: On return the clocks, delay timebase, LED1, and MSTP are live.; On failure control never returns.

Note: Not thread-safe; single-threaded init context.

Since: 0.1.0

Definition at line 236 of file main.c.

References gpt_ecc_panic_halt(), k_ra8_board_led1, k_ra8_clock_id_cpuclk0, k_ra8_ok, ra8_board_led_init(), ra8_cgc_get_clock_hz(), ra8_cgc_init(), ra8_mstp_init(), and ra8_time_init().

Referenced by main().

◆ gpt_ecc_panic_halt()

void gpt_ecc_panic_halt ( void )

static

Park the CPU after a fatal init failure.

Spins in a low-power wait so a debugger can inspect state.

Precondition: A setup step returned an error.; No further progress is safe.

Postcondition: Control never returns to the caller.; No registers are modified.

Note: Not thread-safe; terminal path.

Since: 0.1.0

Definition at line 186 of file main.c.

Referenced by gpt_ecc_clocks_or_halt(), gpt_ecc_route_pins_or_halt(), gpt_ecc_timers_or_halt(), and main().

◆ gpt_ecc_period_valid()

bool gpt_ecc_period_valid ( uint32_t delta_ticks )

static

Classify a captured delta as a genuine signal period.

Windows the delta to reject noise (too short) and the first / wrapped latch (too long). This is the demo's one compound decision.

Parameters

[in] delta_ticks Difference between two consecutive GTCCRA latches, in GPT counter ticks (0 .. UINT32_MAX).

Returns: true when k_gpt_ecc_min_valid_ticks <= delta_ticks <= k_gpt_ecc_max_valid_ticks, false otherwise.

Precondition: The two source latches came from an armed capture register.; delta_ticks was computed as an unsigned subtraction.

Postcondition: No state is modified (pure predicate).; The return reflects only delta_ticks.

MC/DC:: Compound decision (delta >= min) && (delta <= max) – two conditions, N+1 = 3 vectors (in-window true; below-floor false; above-ceiling false). The companion host test tests/mocks/src/test_app_gpt_edge_capture_count.c exercises each vector.

Note: Thread safety: reentrant (no shared state).

Since: 0.1.0

Definition at line 218 of file main.c.

References k_gpt_ecc_max_valid_ticks, and k_gpt_ecc_min_valid_ticks.

Referenced by gpt_ecc_service_capture().

◆ gpt_ecc_route_pins_or_halt()

void gpt_ecc_route_pins_or_halt ( void )

static

Route the two GTIOCnA edge-input pins to the GPT peripheral.

Uses ra8_pfs_route_peripheral with PSEL k_ra8_psel_gpt0 (GPT channels 0..3). Any failure halts.

Precondition: gpt_ecc_clocks_or_halt has run.; The placeholder pins are conflict-free (see TODO board-rev).

Postcondition: On return GTIOC0A / GTIOC1A are muxed to the GPT.; On failure control never returns.

Note: Not thread-safe; single-threaded init context.

Since: 0.1.0

Definition at line 268 of file main.c.

References gpt_ecc_panic_halt(), k_gpt_ecc_pin_capture, k_gpt_ecc_pin_count, k_ra8_ok, k_ra8_psel_gpt0, and ra8_pfs_route_peripheral().

Referenced by main().

◆ gpt_ecc_service_capture()

bool gpt_ecc_service_capture ( uint32_t * prev_latch )

static

Service one input-capture poll: latch delta -> globals.

Checks GTST.TCFA; on a fresh latch reads GTCCRA, computes the delta from *prev_latch, and on a valid period updates the published globals and toggles LED1. Clears TCFA before returning.

Parameters

[in,out] prev_latch Previous GTCCRA latch value; updated to the current latch when a capture is serviced.

Returns: true when a fresh capture edge was serviced, false otherwise.

Precondition: gpt_ecc_timers_or_halt armed the capture channel.; prev_latch points to writable storage.

Postcondition: *prev_latch holds the newest latch when true is returned.; GTST.TCFA is cleared when a capture was serviced.

Note: Not thread-safe; called only from the main loop.

Since: 0.1.0

Definition at line 345 of file main.c.

References g_gpt_ecc_capture_events, g_gpt_ecc_last_period, gpt_ecc_period_valid(), k_gpt_ecc_capture_channel, k_ra8_board_led1, k_ra8_gpt_ccr_a, k_ra8_gpt_status_ccra, k_ra8_ok, ra8_board_led_toggle(), ra8_gpt_capture_read(), ra8_gpt_clear_status(), and ra8_gpt_get_status().

Referenced by main().

◆ gpt_ecc_timers_or_halt()

void gpt_ecc_timers_or_halt ( void )

static

Configure the capture (GPT0) and count (GPT1) timer channels.

GPT0 starts free-running and GTICASR is armed for GTIOC0A rising-edge capture (#185). GPT1 starts and GTUPSR is armed for GTIOC1A rising-edge counting (#186). Any failure halts.

Precondition: gpt_ecc_route_pins_or_halt has run.; The GPT block clock is enabled by ra8_gpt_init.

Postcondition: On return both channels are counting; capture / count sources are armed.; On failure control never returns.

Note: Not thread-safe; single-threaded init context.

Since: 0.1.0

Definition at line 295 of file main.c.

References gpt_ecc_panic_halt(), k_gpt_ecc_capture_channel, k_gpt_ecc_count_channel, k_gpt_ecc_period, k_ra8_gpt_cap_src_ioca_rising, k_ra8_gpt_ccr_a, k_ra8_gpt_cnt_src_ioca_rising, k_ra8_gpt_cnt_src_none, k_ra8_gpt_mode_saw_pwm, k_ra8_gpt_ps_div_1, k_ra8_ok, ra8_gpt_capture_configure(), ra8_gpt_event_count_configure(), and ra8_gpt_init().

Referenced by main().

◆ main()

void main ( void )

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has configured the clock tree and VTOR.

Postcondition: Control does not return; the image runs until reset or halt.; Any value the application wanted to report has been logged, not returned.

Note: Not thread-safe; single-threaded startup context only.

Warning: Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.

See also: SystemInit()

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the playback loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the sweep loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.

Postcondition: On clean entry the kernel runs the worker thread once.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the kernel runs the worker thread forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition: Reset_Handler has copied .data + zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: CPUCLK0 is raised to the PLL1 target before the kernel starts.; On clean entry the SD card thread runs forever.; On any HAL init failure the function halts in __WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the iso-IN feed loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition: Boot init has completed.; The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).

Postcondition: Diagnostic counter latched, CPU parked in a halt loop.; Function never returns.

Note: Single-threaded entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.; On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.; On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.

Postcondition: The shelf scans on the panel; taps open books, browse, and read.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The slab/arena/tile/vmem banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the cache globals are latched and g_pc_heartbeat advances.; On any failure g_pc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Profiles power modes once a second.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the profile + blink loop.; On any HAL hard error LED2 latches ON.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; The shared board boot files installed the vector table.

Postcondition: The demo has run once and its verdict banner is streaming steadily.; The CPU idles re-emitting the banner (or halts after a fatal init error).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, SPI, and SD card, then runs the shared ra8_io VFS round-trip over the SD-over-SPI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the CPU loops forever after the PASS banner.; On any failure the function prints FAIL and halts in WFI.

Note: Not thread-safe; this is the single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging and the console, brings up the OSPI NOR volume, runs the erase-before-write round-trip, and prints a single PASS/FAIL verdict line over SCI8 before parking in an infinite loop.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition: Exactly one PASS or FAIL verdict line has been queued on SCI8.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The page-count + render-hash banner is emitted; the CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The cal=OK / cal=SKIP result and the finger-free touchcal: ready sentinel are emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The open=OK touch banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Both USB controllers' clocks and pins come up before the kernel so the workers only deal with stack bring-up.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: On clean entry the CPU stays in tx_kernel_enter forever.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging and the clock tree, releases the Cortex-M33 (which then blinks LED1 via ra8_pcntr_set_output()), and idles. See the file header.

Precondition: SystemInit has completed core bring-up.; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and is blinking LED1.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: The application links ra8_c6link and ESP-hosted generated codecs.; No hardware validation is inferred from this function.

Postcondition: No c6link operation is attempted.; No network or storage state is modified.

Note: Single-threaded compile fixture.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the cacheable-SRAM round-trip with the D-cache that SystemInit() enabled through ra8_cache_dcache_enable(), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU + RA8_BOOT_CACHE_VIA_HAL).

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + I-cache + D-cache via the ra8_cache HAL.

Postcondition: Exactly one banner (PASS or FAIL) has been emitted.; The core is parked in WFI.

Note: Single-threaded; no RTOS and no IRQ sources in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, releases the Cortex-M33 into the emitter, yields until it signals done, validates the blob the M33 built, then logs the PASS/FAIL verdict and the chapter count read back from the blob. See the file header for the offload narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 has built a RABOOK1 blob and the M85 has validated it.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the CPU heartbeats after epaper: PASS.; On any HAL error the console prints epaper: FAIL and the red LED latches on.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The chapters/toc/cover banner is emitted; CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The reader loop runs forever, redrawing on each tap.; A page-1 banner is emitted once after the first render.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The cover-size / framebuffer-CRC banner is emitted; CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The panel shows the reader screen and the input loop runs forever.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, arms the IPC0 wake and configures the LPM block, releases the Cortex-M33 into the reader, waits for the first held page, logs the page-0 verdict, then runs the #150 mode-switch cycle – parking in low-power WFI and waking on the M33's page-turn pokes – before logging the handoff verdict and parking for good. See the file header for the narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 has rendered + re-rendered the held page and the M85 is parked.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The boot banner is emitted; the reader loop services taps forever.

Since: 0.1.0

Definition at line 369 of file main.c.

References g_gpt_ecc_pulse_count, g_gpt_ecc_tick, gpt_ecc_clocks_or_halt(), gpt_ecc_panic_halt(), gpt_ecc_route_pins_or_halt(), gpt_ecc_service_capture(), gpt_ecc_timers_or_halt(), k_gpt_ecc_capture_channel, k_gpt_ecc_count_channel, k_gpt_ecc_poll_period_ms, k_ra8_ok, ra8_delay_ms(), ra8_gpt_read(), and ra8_isr_globals_enable().

Variable Documentation

◆ g_gpt_ecc_capture_events

volatile uint32_t g_gpt_ecc_capture_events = 0U

Count of valid input-capture edges observed so far.

Note: Read externally by J-Link / a future HIL probe.

Warning: Written from the main loop; do not modify externally.

Since: 0.1.0

Definition at line 147 of file main.c.

Referenced by gpt_ecc_service_capture().

◆ g_gpt_ecc_last_period

volatile uint32_t g_gpt_ecc_last_period = 0U

Most recent valid input-capture delta, in GPT counter ticks.

Updated only when a captured delta passes gpt_ecc_period_valid. Zero until the first valid capture.

Note: Read externally by J-Link / a future HIL probe.

Warning: Written from the main loop; do not modify externally.

Since: 0.1.0

Definition at line 137 of file main.c.

Referenced by gpt_ecc_service_capture().

◆ g_gpt_ecc_pulse_count

volatile uint32_t g_gpt_ecc_pulse_count = 0U

Latest accumulated external pulse count (GPT1 GTCNT).

Reflects GTUPSR-driven event counting: the number of external rising edges the count channel has tallied.

Note: Read externally by J-Link / a future HIL probe.

Warning: Written from the main loop; do not modify externally.

Since: 0.1.0

Definition at line 159 of file main.c.

Referenced by main().

◆ g_gpt_ecc_tick

volatile uint32_t g_gpt_ecc_tick = 0U

Pin-independent liveness counter.

Bumped whenever the capture channel's free-running GTCNT advanced between two samples. Proves the GPT counter is alive even when no edge source is wired (the unattended-bench case), separately from the pin-driven capture / count signals above.

Note: Read externally by J-Link / a future HIL probe.

Warning: Written from the main loop; do not modify externally.

Since: 0.1.0

Definition at line 173 of file main.c.

Referenced by main().

◆ k_gpt_ecc_pin_capture

const ra8_port_pin_t k_gpt_ecc_pin_capture = ((ra8_port_pin_t)(((uint16_t)(k_ra8_port_4) << 8) | (uint16_t)(k_ra8_pin_8)))

static

GTIOC0A input pad for the capture channel (placeholder).

TODO(board-rev): the EK-RA8D2 breaks out no conflict-free GTIOC0A pad – the candidate pins overlap the debug UART per HUM Ch 20.6 pin tables. This P408 assignment is illustrative so the app builds and the ra8_pfs_route_peripheral call is exercised; update it (or move to a carrier board) before bench validation.

Note: Consumed by gpt_ecc_route_pins_or_halt.

Since: 0.1.0

Definition at line 113 of file main.c.

Referenced by gpt_ecc_route_pins_or_halt().

◆ k_gpt_ecc_pin_count

const ra8_port_pin_t k_gpt_ecc_pin_count = ((ra8_port_pin_t)(((uint16_t)(k_ra8_port_4) << 8) | (uint16_t)(k_ra8_pin_9)))

static

GTIOC1A input pad for the event-count channel (placeholder).

TODO(board-rev): same EK-RA8D2 pad-availability caveat as k_gpt_ecc_pin_capture; P409 is illustrative.

Note: Consumed by gpt_ecc_route_pins_or_halt.

Since: 0.1.0

Definition at line 125 of file main.c.

Referenced by gpt_ecc_route_pins_or_halt().

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ gpt_ecc_layout_t

◆ gpt_ecc_period_const_t

◆ gpt_ecc_poll_const_t

Function Documentation

◆ gpt_ecc_clocks_or_halt()

◆ gpt_ecc_panic_halt()

◆ gpt_ecc_period_valid()

◆ gpt_ecc_route_pins_or_halt()

◆ gpt_ecc_service_capture()

◆ gpt_ecc_timers_or_halt()

◆ main()

Variable Documentation

◆ g_gpt_ecc_capture_events

◆ g_gpt_ecc_last_period

◆ g_gpt_ecc_pulse_count

◆ g_gpt_ecc_tick

◆ k_gpt_ecc_pin_capture

◆ k_gpt_ecc_pin_count