86typedef enum : uint8_t {
99typedef enum : uint8_t {
114typedef enum : uint16_t {
130typedef enum : uint8_t {
144typedef enum : uint8_t {
723 uint32_t compare_match,
ra8_board_eth_pin_t pin
Pin.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
ra8_err_t ra8_pdg_delay_ns_to_code(uint32_t delay_ns, uint32_t gptclk_hz, ra8_pdg_frange_t frange, uint8_t *out_code)
Convert a desired pin-to-pin delay (in nanoseconds) to a DLY[6:0] code given a measured GPTCLK freque...
ra8_err_t ra8_pdg_pin_disable(uint8_t channel, ra8_pdg_pin_t pin)
Force a single A or B pin's delay to zero (per-pin disable) without touching the channel-level bypass...
ra8_err_t ra8_pdg_set_frange(ra8_pdg_frange_t new_frange)
Switch FRANGE at runtime, re-running the DLL re-lock sequence with the new band.
ra8_err_t ra8_pdg_exit_stop(uint8_t channel)
Power up one PDG channel (clear the GTDLYCR2.DLYENn bit).
ra8_err_t ra8_pdg_clear_status(uint16_t mask)
Clear the soft-reset bit (DLYRST -> 0) and re-enable the DLL.
ra8_err_t ra8_pdg_attach_handler(ra8_pdg_event_fn_t fn, void *ctx)
Attach an asynchronous PDG event callback.
ra8_err_t ra8_pdg_channel_bypass_set(uint8_t channel, uint8_t bypass)
Set or clear the bypass bit for a channel.
ra8_err_t ra8_pdg_bind_gpt_channel(uint8_t channel)
Bind PDG channel n to its host GPT32n channel.
ra8_err_t ra8_pdg_set_delay(uint8_t channel, ra8_pdg_pin_t pin, ra8_pdg_edge_t edge, uint8_t code)
Set the per-edge fine delay for one PDG channel/pin/edge.
ra8_pdg_wave_mode_t
PWM waveform shape – selects which Table 23.4 row applies.
@ k_ra8_pdg_wave_saw
Saw-wave PWM (count up or down).
@ k_ra8_pdg_wave_triangle
Triangle-wave PWM.
ra8_err_t ra8_pdg_capture_start(const ra8_pdg_delay_entry_t *buf, uint8_t len)
Stage a buffer of ra8_pdg_delay_entry_t records and arm them.
ra8_err_t ra8_pdg_set_delay_batch(const ra8_pdg_delay_entry_t *entries, uint8_t count)
Atomically program a batch of (channel, pin, edge, code) delay updates.
ra8_err_t ra8_pdg_get_delay(uint8_t channel, ra8_pdg_pin_t pin, ra8_pdg_edge_t edge, uint8_t *out_code)
Read back the last-programmed delay code.
ra8_err_t ra8_pdg_pick_frange(uint32_t gptclk_hz, ra8_pdg_frange_t *out)
Auto-pick a FRANGE value from a measured GPTCLK frequency.
ra8_pdg_edge_t
Selects which delay register family is targeted.
@ k_ra8_pdg_edge_rising
GTDLYRnA / GTDLYRnB.
@ k_ra8_pdg_edge_falling
GTDLYFnA / GTDLYFnB.
void(* ra8_pdg_event_fn_t)(void *ctx)
PDG event callback (DLL lock event, etc.).
ra8_err_t ra8_pdg_get_status(uint16_t *out)
Read GTDLYCR packed into a status mask.
ra8_err_t ra8_pdg_required_write_ns(uint32_t pclka_hz, uint32_t gptclk_hz, uint32_t *out_ns)
Compute the minimum register-write interval (HUM 23.4.3 p 1163).
ra8_pdg_status_t
Bits surfaced by ra8_pdg_get_status (legacy compact form).
@ k_ra8_pdg_status_dll_locked
DLLEN = 1 (DLL running).
@ k_ra8_pdg_status_frange_msk
Live FRANGE[1:0] bits.
@ k_ra8_pdg_status_in_reset
DLYRST = 1 (held in reset).
ra8_err_t ra8_pdg_capture_stop(void)
Cancel any pending buffered apply and clear the completion latch.
ra8_err_t ra8_pdg_enter_stop(uint8_t channel)
Power down one PDG channel (set GTDLYCR2.DLYENn).
ra8_err_t ra8_pdg_get_status_full(ra8_pdg_status_full_t *out)
Read a fully-decoded snapshot of GTDLYCR + GTDLYCR2.
ra8_pdg_pin_t
Picks the A or B pin within a PDG channel.
@ k_ra8_pdg_pin_a
GTIOCnA – "A" output of GPT32n.
@ k_ra8_pdg_pin_b
GTIOCnB – "B" output of GPT32n.
ra8_pdg_count_dir_t
Counter direction passed to ra8_pdg_check_constraints.
@ k_ra8_pdg_dir_up
Counter is up-counting (TUCF == 0).
@ k_ra8_pdg_dir_down
Counter is down-counting (TUCF == 1).
ra8_err_t ra8_pdg_deinit(void)
Tear down the PDG block (reset + module-stop).
ra8_err_t ra8_pdg_init(const ra8_pdg_config_t *cfg)
Initialise the PDG block per HUM Figure 23.2 (p 1160).
ra8_err_t ra8_pdg_unbind_gpt_channel(uint8_t channel)
Reverse ra8_pdg_bind_gpt_channel, restoring write-protect.
void ra8_pdg_dispatch(void)
Fire the registered handler.
ra8_err_t ra8_pdg_check_constraints(ra8_pdg_wave_mode_t mode, ra8_pdg_count_dir_t dir, uint32_t compare_match, uint32_t gtpr)
Check Table 23.4 constraints before writing a delay register.
PWM Delay Generation Circuit (PDG) register layout for the Renesas RA8D2.
@ k_ra8_pdg_channel_count
4 GPT channels mapped to PDG (0..3).
ra8_pdg_frange_t
GTDLYCR.FRANGE encoding (HUM Ch 23.2.1 p 1154).
Driver configuration descriptor for ra8_pdg_init.
uint32_t gptclk_hz
Measured GTCLK frequency (Hz).
ra8_pdg_frange_t frange
GPT core clock band (HUM 23.2.1).
uint8_t channel_mask
Bit n = enable PDG channel n.
uint8_t auto_tune
1 = ignore frange, derive from gptclk_hz.
Single-edge descriptor for the batch update API.
ra8_pdg_edge_t edge
Rising or falling.
uint8_t code
DLY[6:0] code, 0..0x7F.
ra8_pdg_pin_t pin
k_ra8_pdg_pin_a / k_ra8_pdg_pin_b.
Decoded snapshot of GTDLYCR / GTDLYCR2 returned by ra8_pdg_get_status_full.
uint16_t raw_gtdlycr2
Raw GTDLYCR2 contents.
uint8_t per_channel_powered[k_ra8_pdg_channel_count]
!DLYENn.
uint8_t in_reset
GTDLYCR.DLYRST.
ra8_pdg_frange_t frange
GTDLYCR.FRANGE[1:0].
uint8_t per_channel_bypass_off[k_ra8_pdg_channel_count]
DLYBSn.
uint8_t dll_enabled
GTDLYCR.DLLEN.
uint16_t raw_gtdlycr
Raw GTDLYCR contents.