ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_pdg.h
Go to the documentation of this file.
1
65
66#pragma once
67
68#ifdef __cplusplus
69extern "C" {
70#endif
71
72#include <stdint.h>
73
74#include "ra8_err.h"
75#include "ra8_pdg_regs.h"
76
86typedef enum : uint8_t {
90
99typedef enum : uint8_t {
103
119
130typedef enum : uint8_t {
134
148
179
200
217
231typedef void (*ra8_pdg_event_fn_t)(void* ctx);
232
233/* =============================================================================
234 * Lifecycle
235 * =============================================================================
236 */
237
272[[nodiscard]] ra8_err_t ra8_pdg_init(const ra8_pdg_config_t* cfg);
273
288[[nodiscard]] ra8_err_t ra8_pdg_deinit(void);
289
290/* =============================================================================
291 * Per-edge delay programming
292 * =============================================================================
293 */
294
325[[nodiscard]] ra8_err_t
326ra8_pdg_set_delay(uint8_t channel, ra8_pdg_pin_t pin, ra8_pdg_edge_t edge, uint8_t code);
327
345[[nodiscard]] ra8_err_t
346ra8_pdg_get_delay(uint8_t channel, ra8_pdg_pin_t pin, ra8_pdg_edge_t edge, uint8_t* out_code);
347
379[[nodiscard]] ra8_err_t ra8_pdg_set_delay_batch(const ra8_pdg_delay_entry_t* entries,
380 uint8_t count);
381
408[[nodiscard]] ra8_err_t ra8_pdg_delay_ns_to_code(uint32_t delay_ns,
409 uint32_t gptclk_hz,
410 ra8_pdg_frange_t frange,
411 uint8_t* out_code);
412
413/* =============================================================================
414 * Per-channel and per-pin power transition
415 * =============================================================================
416 */
417
431[[nodiscard]] ra8_err_t ra8_pdg_exit_stop(uint8_t channel);
432
446[[nodiscard]] ra8_err_t ra8_pdg_enter_stop(uint8_t channel);
447
468[[nodiscard]] ra8_err_t ra8_pdg_channel_bypass_set(uint8_t channel, uint8_t bypass);
469
490[[nodiscard]] ra8_err_t ra8_pdg_pin_disable(uint8_t channel, ra8_pdg_pin_t pin);
491
492/* =============================================================================
493 * Status / IRQ
494 * =============================================================================
495 */
496
509[[nodiscard]] ra8_err_t ra8_pdg_get_status(uint16_t* out);
510
527
548[[nodiscard]] ra8_err_t ra8_pdg_clear_status(uint16_t mask);
549
569[[nodiscard]] ra8_err_t ra8_pdg_attach_handler(ra8_pdg_event_fn_t fn, void* ctx);
570
583void ra8_pdg_dispatch(void);
584
585/* =============================================================================
586 * Runtime FRANGE switch + auto-tune calibration
587 * =============================================================================
588 */
589
614[[nodiscard]] ra8_err_t ra8_pdg_pick_frange(uint32_t gptclk_hz, ra8_pdg_frange_t* out);
615
644[[nodiscard]] ra8_err_t ra8_pdg_set_frange(ra8_pdg_frange_t new_frange);
645
646/* =============================================================================
647 * GPT0/1/2/3 binding helpers
648 * =============================================================================
649 */
650
673[[nodiscard]] ra8_err_t ra8_pdg_bind_gpt_channel(uint8_t channel);
674
687[[nodiscard]] ra8_err_t ra8_pdg_unbind_gpt_channel(uint8_t channel);
688
689/* =============================================================================
690 * Constraint validation (HUM Ch 23.4.2 / 23.4.3)
691 * =============================================================================
692 */
693
723 uint32_t compare_match,
724 uint32_t gtpr);
725
747[[nodiscard]] ra8_err_t
748ra8_pdg_required_write_ns(uint32_t pclka_hz, uint32_t gptclk_hz, uint32_t* out_ns);
749
750/* =============================================================================
751 * Sweep 17: capture-style buffered delay-code apply + completion callback
752 * =============================================================================
753 */
754
787[[nodiscard]] ra8_err_t ra8_pdg_capture_start(const ra8_pdg_delay_entry_t* buf, uint8_t len);
788
807[[nodiscard]] ra8_err_t ra8_pdg_capture_stop(void);
808
809#ifdef __cplusplus
810}
811#endif
ra8_board_eth_pin_t pin
Pin.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
ra8_err_t ra8_pdg_delay_ns_to_code(uint32_t delay_ns, uint32_t gptclk_hz, ra8_pdg_frange_t frange, uint8_t *out_code)
Convert a desired pin-to-pin delay (in nanoseconds) to a DLY[6:0] code given a measured GPTCLK freque...
Definition ra8_pdg.c:554
ra8_err_t ra8_pdg_pin_disable(uint8_t channel, ra8_pdg_pin_t pin)
Force a single A or B pin's delay to zero (per-pin disable) without touching the channel-level bypass...
Definition ra8_pdg.c:637
ra8_err_t ra8_pdg_set_frange(ra8_pdg_frange_t new_frange)
Switch FRANGE at runtime, re-running the DLL re-lock sequence with the new band.
Definition ra8_pdg.c:787
ra8_err_t ra8_pdg_exit_stop(uint8_t channel)
Power up one PDG channel (clear the GTDLYCR2.DLYENn bit).
Definition ra8_pdg.c:589
ra8_err_t ra8_pdg_clear_status(uint16_t mask)
Clear the soft-reset bit (DLYRST -> 0) and re-enable the DLL.
Definition ra8_pdg.c:696
ra8_err_t ra8_pdg_attach_handler(ra8_pdg_event_fn_t fn, void *ctx)
Attach an asynchronous PDG event callback.
Definition ra8_pdg.c:707
ra8_err_t ra8_pdg_channel_bypass_set(uint8_t channel, uint8_t bypass)
Set or clear the bypass bit for a channel.
Definition ra8_pdg.c:616
ra8_err_t ra8_pdg_bind_gpt_channel(uint8_t channel)
Bind PDG channel n to its host GPT32n channel.
Definition ra8_pdg.c:839
ra8_err_t ra8_pdg_set_delay(uint8_t channel, ra8_pdg_pin_t pin, ra8_pdg_edge_t edge, uint8_t code)
Set the per-edge fine delay for one PDG channel/pin/edge.
Definition ra8_pdg.c:494
ra8_pdg_wave_mode_t
PWM waveform shape – selects which Table 23.4 row applies.
Definition ra8_pdg.h:144
@ k_ra8_pdg_wave_saw
Saw-wave PWM (count up or down).
Definition ra8_pdg.h:145
@ k_ra8_pdg_wave_triangle
Triangle-wave PWM.
Definition ra8_pdg.h:146
ra8_err_t ra8_pdg_capture_start(const ra8_pdg_delay_entry_t *buf, uint8_t len)
Stage a buffer of ra8_pdg_delay_entry_t records and arm them.
Definition ra8_pdg.c:738
ra8_err_t ra8_pdg_set_delay_batch(const ra8_pdg_delay_entry_t *entries, uint8_t count)
Atomically program a batch of (channel, pin, edge, code) delay updates.
Definition ra8_pdg.c:525
ra8_err_t ra8_pdg_get_delay(uint8_t channel, ra8_pdg_pin_t pin, ra8_pdg_edge_t edge, uint8_t *out_code)
Read back the last-programmed delay code.
Definition ra8_pdg.c:512
ra8_err_t ra8_pdg_pick_frange(uint32_t gptclk_hz, ra8_pdg_frange_t *out)
Auto-pick a FRANGE value from a measured GPTCLK frequency.
Definition ra8_pdg.c:765
ra8_pdg_edge_t
Selects which delay register family is targeted.
Definition ra8_pdg.h:86
@ k_ra8_pdg_edge_rising
GTDLYRnA / GTDLYRnB.
Definition ra8_pdg.h:87
@ k_ra8_pdg_edge_falling
GTDLYFnA / GTDLYFnB.
Definition ra8_pdg.h:88
void(* ra8_pdg_event_fn_t)(void *ctx)
PDG event callback (DLL lock event, etc.).
Definition ra8_pdg.h:231
ra8_err_t ra8_pdg_get_status(uint16_t *out)
Read GTDLYCR packed into a status mask.
Definition ra8_pdg.c:663
ra8_err_t ra8_pdg_required_write_ns(uint32_t pclka_hz, uint32_t gptclk_hz, uint32_t *out_ns)
Compute the minimum register-write interval (HUM 23.4.3 p 1163).
Definition ra8_pdg.c:921
ra8_pdg_status_t
Bits surfaced by ra8_pdg_get_status (legacy compact form).
Definition ra8_pdg.h:114
@ k_ra8_pdg_status_dll_locked
DLLEN = 1 (DLL running).
Definition ra8_pdg.h:115
@ k_ra8_pdg_status_frange_msk
Live FRANGE[1:0] bits.
Definition ra8_pdg.h:117
@ k_ra8_pdg_status_in_reset
DLYRST = 1 (held in reset).
Definition ra8_pdg.h:116
ra8_err_t ra8_pdg_capture_stop(void)
Cancel any pending buffered apply and clear the completion latch.
Definition ra8_pdg.c:754
ra8_err_t ra8_pdg_enter_stop(uint8_t channel)
Power down one PDG channel (set GTDLYCR2.DLYENn).
Definition ra8_pdg.c:603
ra8_err_t ra8_pdg_get_status_full(ra8_pdg_status_full_t *out)
Read a fully-decoded snapshot of GTDLYCR + GTDLYCR2.
Definition ra8_pdg.c:672
ra8_pdg_pin_t
Picks the A or B pin within a PDG channel.
Definition ra8_pdg.h:99
@ k_ra8_pdg_pin_a
GTIOCnA – "A" output of GPT32n.
Definition ra8_pdg.h:100
@ k_ra8_pdg_pin_b
GTIOCnB – "B" output of GPT32n.
Definition ra8_pdg.h:101
ra8_pdg_count_dir_t
Counter direction passed to ra8_pdg_check_constraints.
Definition ra8_pdg.h:130
@ k_ra8_pdg_dir_up
Counter is up-counting (TUCF == 0).
Definition ra8_pdg.h:131
@ k_ra8_pdg_dir_down
Counter is down-counting (TUCF == 1).
Definition ra8_pdg.h:132
ra8_err_t ra8_pdg_deinit(void)
Tear down the PDG block (reset + module-stop).
Definition ra8_pdg.c:464
ra8_err_t ra8_pdg_init(const ra8_pdg_config_t *cfg)
Initialise the PDG block per HUM Figure 23.2 (p 1160).
Definition ra8_pdg.c:438
ra8_err_t ra8_pdg_unbind_gpt_channel(uint8_t channel)
Reverse ra8_pdg_bind_gpt_channel, restoring write-protect.
Definition ra8_pdg.c:860
void ra8_pdg_dispatch(void)
Fire the registered handler.
Definition ra8_pdg.c:715
ra8_err_t ra8_pdg_check_constraints(ra8_pdg_wave_mode_t mode, ra8_pdg_count_dir_t dir, uint32_t compare_match, uint32_t gtpr)
Check Table 23.4 constraints before writing a delay register.
Definition ra8_pdg.c:881
PWM Delay Generation Circuit (PDG) register layout for the Renesas RA8D2.
@ k_ra8_pdg_channel_count
4 GPT channels mapped to PDG (0..3).
ra8_pdg_frange_t
GTDLYCR.FRANGE encoding (HUM Ch 23.2.1 p 1154).
Driver configuration descriptor for ra8_pdg_init.
Definition ra8_pdg.h:173
uint32_t gptclk_hz
Measured GTCLK frequency (Hz).
Definition ra8_pdg.h:177
ra8_pdg_frange_t frange
GPT core clock band (HUM 23.2.1).
Definition ra8_pdg.h:174
uint8_t channel_mask
Bit n = enable PDG channel n.
Definition ra8_pdg.h:175
uint8_t auto_tune
1 = ignore frange, derive from gptclk_hz.
Definition ra8_pdg.h:176
Single-edge descriptor for the batch update API.
Definition ra8_pdg.h:211
uint8_t channel
0..3.
Definition ra8_pdg.h:212
ra8_pdg_edge_t edge
Rising or falling.
Definition ra8_pdg.h:214
uint8_t code
DLY[6:0] code, 0..0x7F.
Definition ra8_pdg.h:215
ra8_pdg_pin_t pin
k_ra8_pdg_pin_a / k_ra8_pdg_pin_b.
Definition ra8_pdg.h:213
Decoded snapshot of GTDLYCR / GTDLYCR2 returned by ra8_pdg_get_status_full.
Definition ra8_pdg.h:191
uint16_t raw_gtdlycr2
Raw GTDLYCR2 contents.
Definition ra8_pdg.h:198
uint8_t per_channel_powered[k_ra8_pdg_channel_count]
!DLYENn.
Definition ra8_pdg.h:196
uint8_t in_reset
GTDLYCR.DLYRST.
Definition ra8_pdg.h:193
ra8_pdg_frange_t frange
GTDLYCR.FRANGE[1:0].
Definition ra8_pdg.h:194
uint8_t per_channel_bypass_off[k_ra8_pdg_channel_count]
DLYBSn.
Definition ra8_pdg.h:195
uint8_t dll_enabled
GTDLYCR.DLLEN.
Definition ra8_pdg.h:192
uint16_t raw_gtdlycr
Raw GTDLYCR contents.
Definition ra8_pdg.h:197