63typedef enum : uint32_t {
151 __asm__
volatile(
"wfi");
172 uint32_t cpuclk0_hz = 0U;
295 const uint32_t kExpectedCount = (uint32_t)(
sizeof(kExpected) /
sizeof(kExpected[0]));
296 for (uint32_t i = 0U; i < kExpectedCount; ++i) {
301 if (hz != kExpected[i].expected_hz) {
void main(void)
Secure fallback main entry point.
static ra8_err_t internal_clock_check_pins_init(void)
Configure all three EK-RA8D2 user LEDs as outputs (low).
volatile uint32_t g_clock_check_mismatch
HIL failure counter – incremented whenever any clock-tree readback disagrees with its expected target...
clock_check_period_t
Half-period of the visible blink, in milliseconds.
@ k_clock_check_half_period_ms
Clock check half period ms.
static bool internal_clock_check_verify_all(void)
Verify every clock-tree readback equals its post-PLL target.
static void internal_clock_check_panic_halt(void)
Halt forever in WFI – used as a panic stop on init failure.
volatile uint32_t g_clock_check_match
HIL liveness counter – incremented once per blink iteration when every queried clock-tree domain (CPU...
static ra8_err_t internal_clock_check_pins_toggle_all(void)
Toggle all three LED pins (one HAL call each).
Annotation-attribute framework macros for ra8-firmware.
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
ra8_err_t ra8_board_led_toggle(ra8_board_led_id_t led)
Toggle led's output state.
ra8_err_t ra8_board_led_init(ra8_board_led_id_t led)
Configure led as a digital output, initial level low (off).
@ k_ra8_board_led2
LED2, GREEN, P303 (jumper E26).
@ k_ra8_board_led1
LED1, BLUE, P600 (jumper E27).
@ k_ra8_board_led3
LED3, RED, PA07 (jumper E28).
Boot entry points shared between a vector table and its startup code.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
ra8_clock_id_t
Identifiers for the clock-tree frequencies queryable at runtime.
@ k_ra8_clock_id_pclkc
PCLKC.
@ k_ra8_clock_id_fclk
Flash/MRAM interface clock.
@ k_ra8_clock_id_cpuclk1
Cortex-M33 CPUCLK1.
@ k_ra8_clock_id_pclkd
PCLKD.
@ k_ra8_clock_id_pclkb
PCLKB.
@ k_ra8_clock_id_pclke
PCLKE.
@ k_ra8_clock_id_cpuclk0
Cortex-M85 CPUCLK0.
@ k_ra8_clock_id_mriclk
MRAM bus clock.
@ k_ra8_clock_id_pclka
PCLKA.
@ k_ra8_clock_id_iclk
System ICLK.
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
NVIC + ICU IELSR allocator.
void ra8_isr_globals_enable(void)
Globally enable maskable interrupts (PRIMASK = 0).
Typed Port / Pin Constants for the RA8D2 IOPORT Module.
High-level GPIO helpers on top of the PORT + PFS register layer.
SysTick-based tick counter, delay and timestamp helpers.
ra8_err_t ra8_time_init(uint32_t cpu_hz)
Initialise SysTick for a 1 kHz tick interrupt.
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Named Time Unit Constants for Delay / Timeout / Tick Math.
@ k_ra8_mriclk_hz
MRICLK = PLL1P/4 = 250 MHz (MRAM I/F).
@ k_ra8_pclka_hz
PCLKA = PLL1P/8 = 125 MHz.
@ k_ra8_cpuclk1_hz
CPUCLK1 = PLL1P/4 = 250 MHz.
@ k_ra8_cpuclk0_hz
CPUCLK0 = PLL1P/1 = 1 GHz.
@ k_ra8_pclkb_hz
PCLKB = PLL1P/16 = 62.5 MHz.
@ k_ra8_fclk_hz
FCK (MRPCLK) = PLL1P/8 = 125 MHz.
@ k_ra8_pclkd_hz
PCLKD = PLL1P/4 = 250 MHz.
@ k_ra8_pclke_hz
PCLKE = PLL1P/4 = 250 MHz.
@ k_ra8_pclkc_hz
PCLKC = PLL1P/8 = 125 MHz.
@ k_ra8_iclk_hz
ICLK = PLL1P/4 = 250 MHz.
Pair of (clock id, expected post-PLL frequency in Hz).
uint32_t expected_hz
Target frequency after PLL bring-up.
ra8_clock_id_t id
Clock-tree domain identifier.