68typedef enum : uint8_t {
81typedef enum : uint8_t {
95typedef enum : uint8_t {
546ra8_sram_self_test(uint8_t bank, uint32_t probe_offset,
bool inject_two_bit,
bool* out_caught);
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
ra8_err_t ra8_sram_clear_address(uint8_t bank, uint8_t slot)
Clear the captured EAR address for a single (bank, slot) pair.
ra8_err_t ra8_sram_exit_stop(uint8_t bank)
Re-ungate a single bank's clock (Module-Stop exit).
ra8_err_t ra8_sram_set_wait_state_for_clock(uint32_t iclk_hz, uint32_t iclk_max_hz)
Derive SRAMWTSC.WTEN from an ICLK frequency and program it.
ra8_sram_eccrgn_size_t
Public form of SRAMECCRGNn.ECCRGN (per-bank ECC region size).
@ k_ra8_sram_region_128kb
001b – first 128 KB.
@ k_ra8_sram_region_384kb
011b – first 384 KB.
@ k_ra8_sram_region_512kb
100b – whole 512 KB bank.
@ k_ra8_sram_region_off
000b – no ECC region in this bank.
@ k_ra8_sram_region_256kb
010b – first 256 KB.
ra8_err_t ra8_sram_deinit(void)
Tear down the driver and re-gate each bank.
ra8_err_t ra8_sram_attach_bank_handler(uint8_t bank, ra8_sram_error_fn_t fn, void *ctx)
Attach a per-bank ECC error callback.
ra8_err_t ra8_sram_set_mode(uint8_t bank, const ra8_sram_bank_cfg_t *cfg)
Change the ECC mode of a single bank at runtime.
ra8_err_t ra8_sram_zero_init_bank(uint8_t bank)
Deterministically zero one bank under ECC-no-check.
ra8_err_t ra8_sram_set_boundary(uint8_t bank, uint32_t offset)
Write SRAMSABARn (per-bank Secure/Non-Secure boundary).
ra8_err_t ra8_sram_set_eccrgn(uint8_t bank, ra8_sram_eccrgn_size_t region)
Update only the ECC region size (SRAMECCRGNn) for one bank.
ra8_sram_ecc_mode_t
ECC operating mode for a single SRAM bank.
@ k_ra8_sram_ecc_no_check
ECC encode/correct, no error reporting (10b).
@ k_ra8_sram_ecc_with_chk
Full ECC (11b) – raises NMI / reset.
@ k_ra8_sram_ecc_disabled
ECC off (00b).
ra8_err_t ra8_sram_enter_stop(uint8_t bank)
Re-gate a single bank's clock (Module-Stop entry).
void(* ra8_sram_error_fn_t)(void *ctx, uint8_t bank, bool is_2bit, uintptr_t err_addr)
ECC error callback signature.
ra8_sram_on_error_t
Action taken when ECC error is detected (mirrors SRAMCRn.OAD).
@ k_ra8_sram_on_error_interrupt
Raise NMI on ECC error.
@ k_ra8_sram_on_error_reset
Reset the MCU on ECC error.
ra8_err_t ra8_sram_get_status(ra8_sram_status_t *out)
Snapshot the current ECC error state across all four banks.
ra8_err_t ra8_sram_get_bank_info(uint8_t bank, ra8_sram_bank_info_t *out)
Report the static layout of one bank.
void ra8_sram_dispatch(uint8_t bank, bool is_2bit, uintptr_t err_addr)
Dispatch an ECC error event to the registered handler.
ra8_err_t ra8_sram_init(const ra8_sram_config_t *cfg)
Initialise the SRAM driver and configure each bank.
ra8_err_t ra8_sram_attach_handler(ra8_sram_error_fn_t fn, void *ctx)
Attach the global ECC error callback.
ra8_err_t ra8_sram_set_ecc_security(bool non_secure)
Write SRAMESAR (ECC region security).
uint16_t ra8_sram_dispatch_from_esr(ra8_sram_status_t *out_status)
Read SRAMESR + EAR and dispatch every latched flag.
ra8_err_t ra8_sram_self_test(uint8_t bank, uint32_t probe_offset, bool inject_two_bit, bool *out_caught)
Run the HUM Ch 58.3.4 ECC decoder self-test on one bank.
ra8_err_t ra8_sram_clear_status(uint16_t esr_mask)
Clear the listed ECC error bits in SRAMESR (also clears EAR).
ra8_err_t ra8_sram_set_security(uint32_t sa_mask)
Write SRAMSAR (per-bank register security + WTSC security).
SRAM (with ECC) control / status / security register layout.
@ k_ra8_sram_bank_count
SRAM0, SRAM1, SRAM2, SRAM3.
Per-bank ECC configuration descriptor.
ra8_sram_eccrgn_size_t eccrgn
ECC target region size (SRAMECCRGNn).
ra8_sram_on_error_t on_error
NMI vs Reset on ECC error.
ra8_sram_ecc_mode_t ecc_mode
ECC mode (off / no-check / with-check).
bool zero_init
If true, init() runs the zero-init pass.
bool enable_1bit_latch
Set E1STSEN: latch 1-bit errors.
Static description of one bank.
uintptr_t ecc_base
Absolute Secure base of ECC syndrome.
uint8_t bank
Bank index 0..3.
uintptr_t data_base
Absolute Secure base of data region.
uint32_t ecc_size
Bytes in the ECC syndrome region.
uint32_t data_size
Bytes in the data region.
Top-level driver configuration.
bool apply_security
Touch CPSCU registers if true.
ra8_sram_security_cfg_t security
CPSCU security attribution.
ra8_sram_bank_cfg_t banks[k_ra8_sram_bank_count]
Per-bank settings.
TrustZone security attribution configured at init time.
uint32_t boundary_offset[k_ra8_sram_bank_count]
SRAMSABARn boundary value.
bool ecc_region_ns
SRAMESAR.SRAMESA bit.
bool wtsc_ns
SRAMSAR.SRAMWTSA bit.
bool bank_ns[k_ra8_sram_bank_count]
Bit n -> SRAMSAn = 1 (NS).
Snapshot of ECC error state (filled by ra8_sram_get_status).
uint8_t two_bit_mask
Bit i = SRAMi 2-bit error.
uintptr_t addr_2bit[k_ra8_sram_bank_count]
Captured 2-bit error address per bank.
uintptr_t addr_1bit[k_ra8_sram_bank_count]
Captured 1-bit error address per bank.
uint8_t one_bit_mask
Bit i = SRAMi 1-bit error.
uint16_t raw_esr
Raw SRAMESR value.