ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_sram.h
Go to the documentation of this file.
1
42
43#pragma once
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#include <stdint.h>
50
51#include "ra8_err.h"
52#include "ra8_sram_regs.h"
53
54/* =============================================================================
55 * Configuration types
56 * =============================================================================
57 */
58
73
85
102
118
140
169
170/* =============================================================================
171 * Status / event types
172 * =============================================================================
173 */
174
196
205typedef struct {
206 uint8_t bank;
207 uintptr_t data_base;
208 uint32_t data_size;
209 uintptr_t ecc_base;
210 uint32_t ecc_size;
212
221typedef void (*ra8_sram_error_fn_t)(void* ctx, uint8_t bank, bool is_2bit, uintptr_t err_addr);
222
223/* =============================================================================
224 * Lifecycle
225 * =============================================================================
226 */
227
266[[nodiscard]] ra8_err_t ra8_sram_init(const ra8_sram_config_t* cfg);
267
284[[nodiscard]] ra8_err_t ra8_sram_deinit(void);
285
301[[nodiscard]] ra8_err_t ra8_sram_enter_stop(uint8_t bank);
302
318[[nodiscard]] ra8_err_t ra8_sram_exit_stop(uint8_t bank);
319
320/* =============================================================================
321 * ECC mode set / status / clear
322 * =============================================================================
323 */
324
347[[nodiscard]] ra8_err_t ra8_sram_set_mode(uint8_t bank, const ra8_sram_bank_cfg_t* cfg);
348
367[[nodiscard]] ra8_err_t ra8_sram_set_eccrgn(uint8_t bank, ra8_sram_eccrgn_size_t region);
368
404[[nodiscard]] ra8_err_t ra8_sram_set_wait_state_for_clock(uint32_t iclk_hz, uint32_t iclk_max_hz);
405
424
444[[nodiscard]] ra8_err_t ra8_sram_clear_status(uint16_t esr_mask);
445
465[[nodiscard]] ra8_err_t ra8_sram_clear_address(uint8_t bank, uint8_t slot);
466
467/* =============================================================================
468 * Zero-init / self-test / introspection
469 * =============================================================================
470 */
471
505[[nodiscard]] ra8_err_t ra8_sram_zero_init_bank(uint8_t bank);
506
545[[nodiscard]] ra8_err_t
546ra8_sram_self_test(uint8_t bank, uint32_t probe_offset, bool inject_two_bit, bool* out_caught);
547
566[[nodiscard]] ra8_err_t ra8_sram_get_bank_info(uint8_t bank, ra8_sram_bank_info_t* out);
567
568/* =============================================================================
569 * TrustZone security attribution
570 * =============================================================================
571 */
572
590[[nodiscard]] ra8_err_t ra8_sram_set_security(uint32_t sa_mask);
591
606[[nodiscard]] ra8_err_t ra8_sram_set_ecc_security(bool non_secure);
607
625[[nodiscard]] ra8_err_t ra8_sram_set_boundary(uint8_t bank, uint32_t offset);
626
627/* =============================================================================
628 * Interrupt / fault path
629 * =============================================================================
630 */
631
649[[nodiscard]] ra8_err_t ra8_sram_attach_handler(ra8_sram_error_fn_t fn, void* ctx);
650
671[[nodiscard]] ra8_err_t
672ra8_sram_attach_bank_handler(uint8_t bank, ra8_sram_error_fn_t fn, void* ctx);
673
698void ra8_sram_dispatch(uint8_t bank, bool is_2bit, uintptr_t err_addr);
699
728
729#ifdef __cplusplus
730}
731#endif
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
ra8_err_t ra8_sram_clear_address(uint8_t bank, uint8_t slot)
Clear the captured EAR address for a single (bank, slot) pair.
Definition ra8_sram.c:717
ra8_err_t ra8_sram_exit_stop(uint8_t bank)
Re-ungate a single bank's clock (Module-Stop exit).
Definition ra8_sram.c:616
ra8_err_t ra8_sram_set_wait_state_for_clock(uint32_t iclk_hz, uint32_t iclk_max_hz)
Derive SRAMWTSC.WTEN from an ICLK frequency and program it.
Definition ra8_sram.c:661
ra8_sram_eccrgn_size_t
Public form of SRAMECCRGNn.ECCRGN (per-bank ECC region size).
Definition ra8_sram.h:95
@ k_ra8_sram_region_128kb
001b – first 128 KB.
Definition ra8_sram.h:97
@ k_ra8_sram_region_384kb
011b – first 384 KB.
Definition ra8_sram.h:99
@ k_ra8_sram_region_512kb
100b – whole 512 KB bank.
Definition ra8_sram.h:100
@ k_ra8_sram_region_off
000b – no ECC region in this bank.
Definition ra8_sram.h:96
@ k_ra8_sram_region_256kb
010b – first 256 KB.
Definition ra8_sram.h:98
ra8_err_t ra8_sram_deinit(void)
Tear down the driver and re-gate each bank.
Definition ra8_sram.c:578
ra8_err_t ra8_sram_attach_bank_handler(uint8_t bank, ra8_sram_error_fn_t fn, void *ctx)
Attach a per-bank ECC error callback.
ra8_err_t ra8_sram_set_mode(uint8_t bank, const ra8_sram_bank_cfg_t *cfg)
Change the ECC mode of a single bank at runtime.
Definition ra8_sram.c:630
ra8_err_t ra8_sram_zero_init_bank(uint8_t bank)
Deterministically zero one bank under ECC-no-check.
Definition ra8_sram.c:742
ra8_err_t ra8_sram_set_boundary(uint8_t bank, uint32_t offset)
Write SRAMSABARn (per-bank Secure/Non-Secure boundary).
ra8_err_t ra8_sram_set_eccrgn(uint8_t bank, ra8_sram_eccrgn_size_t region)
Update only the ECC region size (SRAMECCRGNn) for one bank.
Definition ra8_sram.c:647
ra8_sram_ecc_mode_t
ECC operating mode for a single SRAM bank.
Definition ra8_sram.h:68
@ k_ra8_sram_ecc_no_check
ECC encode/correct, no error reporting (10b).
Definition ra8_sram.h:70
@ k_ra8_sram_ecc_with_chk
Full ECC (11b) – raises NMI / reset.
Definition ra8_sram.h:71
@ k_ra8_sram_ecc_disabled
ECC off (00b).
Definition ra8_sram.h:69
ra8_err_t ra8_sram_enter_stop(uint8_t bank)
Re-gate a single bank's clock (Module-Stop entry).
Definition ra8_sram.c:607
void(* ra8_sram_error_fn_t)(void *ctx, uint8_t bank, bool is_2bit, uintptr_t err_addr)
ECC error callback signature.
Definition ra8_sram.h:221
ra8_sram_on_error_t
Action taken when ECC error is detected (mirrors SRAMCRn.OAD).
Definition ra8_sram.h:81
@ k_ra8_sram_on_error_interrupt
Raise NMI on ECC error.
Definition ra8_sram.h:82
@ k_ra8_sram_on_error_reset
Reset the MCU on ECC error.
Definition ra8_sram.h:83
ra8_err_t ra8_sram_get_status(ra8_sram_status_t *out)
Snapshot the current ECC error state across all four banks.
Definition ra8_sram.c:682
ra8_err_t ra8_sram_get_bank_info(uint8_t bank, ra8_sram_bank_info_t *out)
Report the static layout of one bank.
Definition ra8_sram.c:841
void ra8_sram_dispatch(uint8_t bank, bool is_2bit, uintptr_t err_addr)
Dispatch an ECC error event to the registered handler.
ra8_err_t ra8_sram_init(const ra8_sram_config_t *cfg)
Initialise the SRAM driver and configure each bank.
Definition ra8_sram.c:551
ra8_err_t ra8_sram_attach_handler(ra8_sram_error_fn_t fn, void *ctx)
Attach the global ECC error callback.
ra8_err_t ra8_sram_set_ecc_security(bool non_secure)
Write SRAMESAR (ECC region security).
uint16_t ra8_sram_dispatch_from_esr(ra8_sram_status_t *out_status)
Read SRAMESR + EAR and dispatch every latched flag.
ra8_err_t ra8_sram_self_test(uint8_t bank, uint32_t probe_offset, bool inject_two_bit, bool *out_caught)
Run the HUM Ch 58.3.4 ECC decoder self-test on one bank.
Definition ra8_sram.c:791
ra8_err_t ra8_sram_clear_status(uint16_t esr_mask)
Clear the listed ECC error bits in SRAMESR (also clears EAR).
Definition ra8_sram.c:705
ra8_err_t ra8_sram_set_security(uint32_t sa_mask)
Write SRAMSAR (per-bank register security + WTSC security).
SRAM (with ECC) control / status / security register layout.
@ k_ra8_sram_bank_count
SRAM0, SRAM1, SRAM2, SRAM3.
Per-bank ECC configuration descriptor.
Definition ra8_sram.h:111
ra8_sram_eccrgn_size_t eccrgn
ECC target region size (SRAMECCRGNn).
Definition ra8_sram.h:115
ra8_sram_on_error_t on_error
NMI vs Reset on ECC error.
Definition ra8_sram.h:113
ra8_sram_ecc_mode_t ecc_mode
ECC mode (off / no-check / with-check).
Definition ra8_sram.h:112
bool zero_init
If true, init() runs the zero-init pass.
Definition ra8_sram.h:116
bool enable_1bit_latch
Set E1STSEN: latch 1-bit errors.
Definition ra8_sram.h:114
Static description of one bank.
Definition ra8_sram.h:205
uintptr_t ecc_base
Absolute Secure base of ECC syndrome.
Definition ra8_sram.h:209
uint8_t bank
Bank index 0..3.
Definition ra8_sram.h:206
uintptr_t data_base
Absolute Secure base of data region.
Definition ra8_sram.h:207
uint32_t ecc_size
Bytes in the ECC syndrome region.
Definition ra8_sram.h:210
uint32_t data_size
Bytes in the data region.
Definition ra8_sram.h:208
Top-level driver configuration.
Definition ra8_sram.h:164
bool apply_security
Touch CPSCU registers if true.
Definition ra8_sram.h:167
ra8_sram_security_cfg_t security
CPSCU security attribution.
Definition ra8_sram.h:166
ra8_sram_bank_cfg_t banks[k_ra8_sram_bank_count]
Per-bank settings.
Definition ra8_sram.h:165
TrustZone security attribution configured at init time.
Definition ra8_sram.h:134
uint32_t boundary_offset[k_ra8_sram_bank_count]
SRAMSABARn boundary value.
Definition ra8_sram.h:138
bool ecc_region_ns
SRAMESAR.SRAMESA bit.
Definition ra8_sram.h:137
bool wtsc_ns
SRAMSAR.SRAMWTSA bit.
Definition ra8_sram.h:136
bool bank_ns[k_ra8_sram_bank_count]
Bit n -> SRAMSAn = 1 (NS).
Definition ra8_sram.h:135
Snapshot of ECC error state (filled by ra8_sram_get_status).
Definition ra8_sram.h:189
uint8_t two_bit_mask
Bit i = SRAMi 2-bit error.
Definition ra8_sram.h:192
uintptr_t addr_2bit[k_ra8_sram_bank_count]
Captured 2-bit error address per bank.
Definition ra8_sram.h:194
uintptr_t addr_1bit[k_ra8_sram_bank_count]
Captured 1-bit error address per bank.
Definition ra8_sram.h:193
uint8_t one_bit_mask
Bit i = SRAMi 1-bit error.
Definition ra8_sram.h:191
uint16_t raw_esr
Raw SRAMESR value.
Definition ra8_sram.h:190