Top-level driver configuration. More...

#include <ra8_sram.h>

Collaboration diagram for ra8_sram_config_t:

Data Fields
ra8_sram_bank_cfg_t	banks [k_ra8_sram_bank_count]
	Per-bank settings.
ra8_sram_security_cfg_t	security
	CPSCU security attribution.
bool	apply_security
	Touch CPSCU registers if true.

Detailed Description

Top-level driver configuration.

banks[i] is applied to SRAM bank i (0..3). Banks for which ecc_mode == k_ra8_sram_ecc_disabled simply ungate the module clock and clear SRAMCRn – nothing more.

apply_security selects whether the CPSCU / SRAMSAR / SRAMESAR registers are touched at all. Leaving it false keeps the post-reset (all-Secure) layout.

There is deliberately no wait-state field. SRAMWTSC.WTEN is not a per-application preference: HUM Ch 58.3.7 "Wait State" p 3540 makes it a function of ICLK alone, and getting it wrong is not a performance choice but undefined operation. ra8_cgc_init owns it and programs it from the ICLK it is about to select, in the same window as the MRAM wait-state latches. A wait_state member here would let a zero-initialised config silently clear it after boot, which is exactly how the two ECC demos in this tree were re-breaking their own memory system (tracker #524).

Definition at line 164 of file ra8_sram.h.