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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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Per-bank ECC configuration descriptor. More...
#include <ra8_sram.h>
Data Fields | |
| ra8_sram_ecc_mode_t | ecc_mode |
| ECC mode (off / no-check / with-check). | |
| ra8_sram_on_error_t | on_error |
| NMI vs Reset on ECC error. | |
| bool | enable_1bit_latch |
| Set E1STSEN: latch 1-bit errors. | |
| ra8_sram_eccrgn_size_t | eccrgn |
| ECC target region size (SRAMECCRGNn). | |
| bool | zero_init |
| If true, init() runs the zero-init pass. | |
Per-bank ECC configuration descriptor.
One of these is filled in for each bank the caller wants to enable ECC on. Defaults to ecc_disabled so unfilled banks are no-ops.
Definition at line 111 of file ra8_sram.h.
| ra8_sram_ecc_mode_t ra8_sram_bank_cfg_t::ecc_mode |
ECC mode (off / no-check / with-check).
Definition at line 112 of file ra8_sram.h.
Referenced by internal_configure(), internal_encode_cr(), internal_mecc_configure(), and internal_validate_bank_cfg().
| ra8_sram_eccrgn_size_t ra8_sram_bank_cfg_t::eccrgn |
ECC target region size (SRAMECCRGNn).
Definition at line 115 of file ra8_sram.h.
Referenced by internal_apply_per_bank(), internal_configure(), internal_mecc_configure(), internal_validate_bank_cfg(), and ra8_sram_set_mode().
| bool ra8_sram_bank_cfg_t::enable_1bit_latch |
Set E1STSEN: latch 1-bit errors.
Definition at line 114 of file ra8_sram.h.
Referenced by internal_configure(), internal_encode_cr(), and internal_mecc_configure().
| ra8_sram_on_error_t ra8_sram_bank_cfg_t::on_error |
NMI vs Reset on ECC error.
Definition at line 113 of file ra8_sram.h.
Referenced by internal_configure(), internal_encode_cr(), internal_mecc_configure(), and internal_validate_bank_cfg().
| bool ra8_sram_bank_cfg_t::zero_init |
If true, init() runs the zero-init pass.
Definition at line 116 of file ra8_sram.h.
Referenced by internal_apply_per_bank(), internal_configure(), and internal_mecc_configure().