SRAM (with ECC) control / status / security register layout. More...

#include <stddef.h>
#include <stdint.h>

Include dependency graph for ra8_sram_regs.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	r_sram_regs_t
	Memory layout of the SRAM control window. More...
struct	r_sram_cpscu_regs_t
	Memory layout of the CPSCU SRAM security window. More...

Enumerations
enum	ra8_sram_addr_t : uintptr_t { k_ra8_sram_base_addr = 0x40002000UL , k_ra8_sram_base_addr_ns = 0x50002000UL , k_ra8_sram_cpscu_base_addr = 0x40008000UL , k_ra8_sram_cpscu_base_ns = 0x50008000UL , k_ra8_sram_data_base_addr = 0x22000000UL , k_ra8_sram_data_base_ns = 0x32000000UL }
	Memory-mapped base addresses for the SRAM windows. More...
enum	ra8_sram_bank_offset_t : uint32_t { k_ra8_sram_bank0_data_off = 0x00000000UL , k_ra8_sram_bank1_data_off = 0x00080000UL , k_ra8_sram_bank2_data_off = 0x00100000UL , k_ra8_sram_bank3_data_off = 0x00180000UL , k_ra8_sram_bank012_size = 0x00080000UL , k_ra8_sram_bank3_size = 0x00020000UL }
	Per-bank offsets into the SRAM data alias. More...
enum	ra8_sram_ecc_region_off_t : uint32_t { k_ra8_sram_ecc_bank0_off = 0x001A0000UL , k_ra8_sram_ecc_bank1_off = 0x001B0000UL , k_ra8_sram_ecc_bank2_off = 0x001C0000UL , k_ra8_sram_ecc_bank3_off = 0x001D0000UL , k_ra8_sram_ecc_bank012_sz = 0x00010000UL , k_ra8_sram_ecc_bank3_sz = 0x00004000UL }
	Per-bank offsets into the SRAM ECC syndrome alias. More...
enum	ra8_sram_bank_count_t : uint8_t { k_ra8_sram_bank_count = 4U }
	Number of SRAM banks (SRAM0..SRAM3). More...
enum	ra8_sram_ear_pair_t : uint8_t { k_ra8_sram_ear_pair_count = 2U , k_ra8_sram_ear_slot_1bit = 0U , k_ra8_sram_ear_slot_2bit = 1U }
	Number of error-address registers per bank (1-bit + 2-bit). More...
enum	ra8_sram_ecc_word_t : uint8_t { k_ra8_sram_ecc_word_bytes = 8U , k_ra8_sram_ecc_word_shift = 3U }
	Granularity of ECC-protected SRAM accesses. More...
enum	ra8_sram_fill_pattern_t : uint64_t { k_ra8_sram_zero_init_word = 0x0000000000000000ULL }
	Fill word for the deterministic zero-init pass. More...
enum	ra8_sram_prcr_key_t : uint16_t { k_ra8_sram_prcr_unlock = 0xA501U , k_ra8_sram_prcr_lock = 0xA500U , k_ra8_sram_prcr_kw = 0xA500U , k_ra8_sram_prcr_pr_msk = 0x0001U }
	SRAMPRCR_S/NS half-word values for unlock / lock. More...
enum	ra8_sram_wtsc_mask_t : uint8_t { k_ra8_sram_wtsc_wten = 0x01U , k_ra8_sram_wtsc_msk = 0x01U }
	SRAMWTSC bit masks. More...
enum	ra8_sram_iclk_threshold_t : uint32_t { k_ra8_sram_iclk_threshold_250mhz = 125000000UL , k_ra8_sram_iclk_threshold_200mhz = 100000000UL , k_ra8_sram_iclk_threshold_150mhz = 75000000UL , k_ra8_sram_iclk_max_default = 250000000UL }
	ICLK frequency thresholds where SRAMWTSC.WTEN must flip to 1. More...
enum	ra8_sram_cr_bit_t : uint8_t { k_ra8_sram_cr_bit_oad = 0U , k_ra8_sram_cr_bit_eccmod0 = 2U , k_ra8_sram_cr_bit_eccmod1 = 3U , k_ra8_sram_cr_bit_e1stsen = 4U , k_ra8_sram_cr_bit_tstbyp = 7U }
	SRAMCRn bit positions. More...
enum	ra8_sram_cr_mask_t : uint8_t { k_ra8_sram_cr_mask_oad = 0x01U , k_ra8_sram_cr_mask_eccmod = 0x0CU , k_ra8_sram_cr_mask_e1stsen = 0x10U , k_ra8_sram_cr_mask_tstbyp = 0x80U , k_ra8_sram_cr_mask_all = 0x9DU }
	SRAMCRn bit masks (HUM Ch 58.2.7, p 3532). More...
enum	ra8_sram_cr_eccmod_t : uint8_t { k_ra8_sram_eccmod_disabled = 0x00U , k_ra8_sram_eccmod_no_check = 0x08U , k_ra8_sram_eccmod_with_chk = 0x0CU }
	Encoded SRAMCRn.ECCMOD field values (already shifted to [3:2]). More...
enum	ra8_sram_cr_self_test_t : uint8_t { k_ra8_sram_cr_self_test_phase_write = 0x08U , k_ra8_sram_cr_self_test_phase_bypass = 0x80U , k_ra8_sram_cr_self_test_phase_verify = 0x1CU }
	SRAMCRn values used by the ECC decoder self-test sequence. More...
enum	ra8_sram_eccrgn_value_t : uint8_t { k_ra8_sram_eccrgn_off = 0U , k_ra8_sram_eccrgn_128kb = 1U , k_ra8_sram_eccrgn_256kb = 2U , k_ra8_sram_eccrgn_384kb = 3U , k_ra8_sram_eccrgn_512kb = 4U , k_ra8_sram_eccrgn_field_msk = 0x07U }
	SRAMECCRGNn.ECCRGN field encodings. More...
enum	ra8_sram_esr_bit_t : uint16_t { k_ra8_sram_err_bank0_1bit = 0x0001U , k_ra8_sram_err_bank0_2bit = 0x0002U , k_ra8_sram_err_bank1_1bit = 0x0004U , k_ra8_sram_err_bank1_2bit = 0x0008U , k_ra8_sram_err_bank2_1bit = 0x0010U , k_ra8_sram_err_bank2_2bit = 0x0020U , k_ra8_sram_err_bank3_1bit = 0x0040U , k_ra8_sram_err_bank3_2bit = 0x0080U , k_ra8_sram_err_all_mask = 0x00FFU , k_ra8_sram_err_all_1bit = 0x0055U , k_ra8_sram_err_all_2bit = 0x00AAU }
	SRAMESR / SRAMESCLR bit positions for each bank. More...
enum	ra8_sram_sar_bit_t : uint32_t { k_ra8_sram_sar_bit_sa0 = 0x00000001UL , k_ra8_sram_sar_bit_sa1 = 0x00000002UL , k_ra8_sram_sar_bit_sa2 = 0x00000004UL , k_ra8_sram_sar_bit_sa3 = 0x00000008UL , k_ra8_sram_sar_bit_wtsa = 0x00000100UL , k_ra8_sram_sar_bank_msk = 0x0000000FUL , k_ra8_sram_sar_writable = 0x0000010FUL }
	SRAMSAR bit positions. More...
enum	ra8_sram_esar_bit_t : uint32_t { k_ra8_sram_esar_bit_esa = 0x00000001UL , k_ra8_sram_esar_writable = 0x00000001UL }
	SRAMESAR bit positions. More...
enum	ra8_sram_sabar_limit_t : uint32_t { k_ra8_sram_sabar_align_mask = 0x00001FFFUL , k_ra8_sram_sabar_field_mask = 0x001FE000UL , k_ra8_sram_sabar_bank0_full = 0x00080000UL , k_ra8_sram_sabar_bank1_full = 0x00100000UL , k_ra8_sram_sabar_bank2_full = 0x00180000UL , k_ra8_sram_sabar_bank3_full = 0x001A0000UL }
	Boundary-address limits per bank for SRAMSABARn. More...
enum	ra8_sram_pad_t : uint16_t { k_ra8_sram_pad_wtsc_to_cr = 7U , k_ra8_sram_pad_cr_sparse_bytes = 12U , k_ra8_sram_pad_eccrgn_sparse = 12U , k_ra8_sram_cpscu_pad_sramsar = 0x3ECU , k_ra8_sram_cpscu_pad_after_sabar = 0x100U }
	Reserved-byte gap sizes used inside the SRAM control register block and CPSCU window. More...
enum	ra8_sram_indexed_t : uint8_t { k_ra8_sram_cr_base_off = 0x10U , k_ra8_sram_eccrgn_base_off = 0x30U , k_ra8_sram_sparse_stride = 4U }
	Stride / base offsets for sparse SRAMCR / SRAMECCRGN slots. More...

Functions
static volatile r_sram_regs_t *	ra8_sram_regs (void)
	Get pointer to the (Secure) SRAM control register block.
static volatile r_sram_cpscu_regs_t *	ra8_sram_cpscu_regs (void)
	Get pointer to the (Secure) CPSCU SRAM security register block.
static volatile uint8_t *	ra8_sram_cr_ptr (volatile r_sram_regs_t *regs, uint8_t bank)
	Indexed write helper: SRAMCRn slot.
static volatile uint8_t *	ra8_sram_eccrgn_ptr (volatile r_sram_regs_t *regs, uint8_t bank)
	Indexed write helper: SRAMECCRGNn slot.
static volatile uint64_t *	ra8_sram_bank_data_ptr (uint8_t bank)
	Per-bank data window helper: pointer to the start of the data alias.
static uint32_t	ra8_sram_bank_size_bytes (uint8_t bank)
	Per-bank data-region size in bytes.
static uint32_t	ra8_sram_bank_ecc_size_bytes (uint8_t bank)
	Per-bank ECC syndrome region size in bytes.

Detailed Description

SRAM (with ECC) control / status / security register layout.

Tag: [Ring 3 / HAL] {World: S}

The RA8D2 has a 2 MB on-chip SRAM split into four banks (SRAM0..SRAM3, see HUM Ch 58.1 Table 58.1, p 3527) with optional SEC-DED ECC (64-bit data + 8-bit syndrome).

Three register windows are involved:

Window	Base (Secure)	Base (Non-Secure)	Notes
CPSCU SRAM	0x4000_8000	0x5000_8000	Security attribution.
SRAM ctl	0x4000_2000	0x5000_2000	PRCR / WTSC / CRn / EAR.
SRAM data	0x2200_0000	0x3200_0000	The actual SRAM banks.

The CPSCU window models SRAMSABARn, SRAMSAR and SRAMESAR. The SRAM control window models SRAMPRCR_S/NS, SRAMWTSC, SRAMCRn, SRAMECCRGNn, SRAMESR, SRAMESCLR and SRAMEARnm.

Per HUM Ch 58.2 (p 3527-3537) the control window layout is:

Offset	Name	Width	Purpose
0x00	SRAMPRCR_S	16	Secure write-protect (key 0xA5).
0x04	SRAMPRCR_NS	16	Non-secure write-protect.
0x08	SRAMWTSC	8	Wait-state enable.
0x10	SRAMCR0	8	SRAM0 ECC mode + OAD + E1STSEN.
0x14	SRAMCR1	8	SRAM1 ECC mode + ...
0x18	SRAMCR2	8	SRAM2 ECC mode + ...
0x1C	SRAMCR3	8	SRAM3 ECC mode + ...
0x30	SRAMECCRGN0	8	SRAM0 ECC region size.
0x34	SRAMECCRGN1	8	SRAM1 ECC region size.
0x38	SRAMECCRGN2	8	SRAM2 ECC region size.
0x3C	SRAMECCRGN3	8	SRAM3 ECC region size.
0x40	SRAMESR	16	ECC error status (1bit/2bit).
0x48	SRAMESCLR	16	ECC error status clear.
0x50+	SRAMEAR[n][m]	32	ECC error address.

Per HUM Ch 58.2.1..58.2.3 (p 3527-3530) the CPSCU window layout is:

Offset	Name	Width	Purpose
0x010	SRAMSAR	32	Per-bank register security.
0x400	SRAMSABAR0	32	SRAM0 Secure/NS boundary.
0x404	SRAMSABAR1	32	SRAM1 Secure/NS boundary.
0x408	SRAMSABAR2	32	SRAM2 Secure/NS boundary.
0x40C	SRAMSABAR3	32	SRAM3 Secure/NS boundary.
0x510	SRAMESAR	32	ECC region security attribute.

Per CLAUDE.md the driver never writes these registers via macros – use the ra8_sram_regs() and ra8_sram_cpscu_regs() accessors so the host-side fake can intercept the writes.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_sram_regs.h.

Enumeration Type Documentation

◆ ra8_sram_addr_t

enum ra8_sram_addr_t : uintptr_t

Memory-mapped base addresses for the SRAM windows.

Per HUM Ch 58.2.4 "SRAMPRCR_S", p 3530 the Secure SRAM-control base is 0x4000_2000 and the Non-Secure alias is 0x5000_2000.

Per HUM Ch 58.2.1 "SRAMSABARn", p 3527 the Secure CPSCU base is 0x4000_8000 and the Non-Secure alias is 0x5000_8000.

Per HUM Ch 58.1 Table 58.1, p 3527 the Secure data base for SRAM0 is 0x2200_0000 and the Non-Secure data alias is 0x3200_0000. The driver targets the Secure aliases on the bare-metal v0.x build (TrustZone partitioning happens later).

Enumerator
k_ra8_sram_base_addr	Secure SRAM control window.
k_ra8_sram_base_addr_ns	Non-Secure SRAM control window.
k_ra8_sram_cpscu_base_addr	Secure CPSCU SRAM window.
k_ra8_sram_cpscu_base_ns	Non-Secure CPSCU SRAM window.
k_ra8_sram_data_base_addr	Secure SRAM data alias (bank 0).
k_ra8_sram_data_base_ns	Non-Secure SRAM data alias.

Definition at line 94 of file ra8_sram_regs.h.

◆ ra8_sram_bank_count_t

enum ra8_sram_bank_count_t : uint8_t

Number of SRAM banks (SRAM0..SRAM3).

Per HUM Ch 58.1 Table 58.1, p 3527: SRAM0/1/2 are 512 KB each and SRAM3 is 128 KB.

Enumerator
k_ra8_sram_bank_count	SRAM0, SRAM1, SRAM2, SRAM3.

Definition at line 153 of file ra8_sram_regs.h.

◆ ra8_sram_bank_offset_t

enum ra8_sram_bank_offset_t : uint32_t

Per-bank offsets into the SRAM data alias.

Per HUM Ch 58.1 Table 58.1, p 3527: SRAM0 lives at offset 0, SRAM1 at offset 0x80000, SRAM2 at offset 0x100000, SRAM3 at offset 0x180000. Sizes follow the table column.

Enumerator
k_ra8_sram_bank0_data_off	SRAM0 starts at 0x2200_0000.
k_ra8_sram_bank1_data_off	SRAM1 starts at 0x2208_0000.
k_ra8_sram_bank2_data_off	SRAM2 starts at 0x2210_0000.
k_ra8_sram_bank3_data_off	SRAM3 starts at 0x2218_0000.
k_ra8_sram_bank012_size	512 KB per bank for 0/1/2.
k_ra8_sram_bank3_size	128 KB for SRAM3.

Definition at line 112 of file ra8_sram_regs.h.

◆ ra8_sram_cr_bit_t

enum ra8_sram_cr_bit_t : uint8_t

SRAMCRn bit positions.

Per HUM Ch 58.2.7 "SRAMCRn", p 3532. Layout:

bit 0 OAD 0=interrupt on ECC err, 1=reset
bit 3:2 ECCMOD 00=disabled, 10=no-check, 11=with-check
bit 4 E1STSEN 1=enable 1-bit error update of SRAMESR
bit 7 TSTBYP 1=enable ECC bypass (decoder test)

Enumerator
k_ra8_sram_cr_bit_oad	Operation after error detection.
k_ra8_sram_cr_bit_eccmod0	ECCMOD low bit.
k_ra8_sram_cr_bit_eccmod1	ECCMOD high bit.
k_ra8_sram_cr_bit_e1stsen	1-bit error status enable.
k_ra8_sram_cr_bit_tstbyp	ECC test bypass.

Definition at line 283 of file ra8_sram_regs.h.

◆ ra8_sram_cr_eccmod_t

enum ra8_sram_cr_eccmod_t : uint8_t

Encoded SRAMCRn.ECCMOD field values (already shifted to [3:2]).

Per HUM Ch 58.2.7, p 3532. 01b is reserved and never written.

Enumerator
k_ra8_sram_eccmod_disabled	00b<<2 = 0x00 (ECC off).
k_ra8_sram_eccmod_no_check	10b<<2 = 0x08 (ECC, no check).
k_ra8_sram_eccmod_with_chk	11b<<2 = 0x0C (ECC + checking).

Definition at line 310 of file ra8_sram_regs.h.

◆ ra8_sram_cr_mask_t

enum ra8_sram_cr_mask_t : uint8_t

SRAMCRn bit masks (HUM Ch 58.2.7, p 3532).

Enumerator
k_ra8_sram_cr_mask_oad	OAD bit 0.
k_ra8_sram_cr_mask_eccmod	ECCMOD[1:0] @ [3:2].
k_ra8_sram_cr_mask_e1stsen	E1STSEN bit 4.
k_ra8_sram_cr_mask_tstbyp	TSTBYP bit 7.
k_ra8_sram_cr_mask_all	Union of the four R/W bits above.

Definition at line 295 of file ra8_sram_regs.h.

◆ ra8_sram_cr_self_test_t

enum ra8_sram_cr_self_test_t : uint8_t

SRAMCRn values used by the ECC decoder self-test sequence.

Per HUM Ch 58.3.4 "ECC Decoder Testing", p 3539, the test flowchart writes three specific bytes to SRAMCRn:

0x08 : ECC enabled, no error checking, bypass disabled (used to write data with valid ECC syndromes).
0x80 : ECC disabled, bypass enabled (used to read/flip the raw ECC syndrome bits).
0x1C : ECC enabled with checking, E1STSEN=1, bypass disabled (used for the verification readback that triggers the expected SRAMESR flag).

Enumerator
k_ra8_sram_cr_self_test_phase_write	ECCMOD=10, all others 0.
k_ra8_sram_cr_self_test_phase_bypass	TSTBYP=1, ECCMOD=00.
k_ra8_sram_cr_self_test_phase_verify	ECCMOD=11, E1STSEN=1.

Definition at line 332 of file ra8_sram_regs.h.

◆ ra8_sram_ear_pair_t

enum ra8_sram_ear_pair_t : uint8_t

Number of error-address registers per bank (1-bit + 2-bit).

Per HUM Ch 58.2.14 "SRAMEARnm", p 3537: m=0 captures the offset of the first 1-bit ECC error in bank n; m=1 captures the first 2-bit error. The pair count is therefore 2.

Enumerator
k_ra8_sram_ear_pair_count	[bank][1-bit, 2-bit].
k_ra8_sram_ear_slot_1bit	SRAMEARn0 – first 1-bit error.
k_ra8_sram_ear_slot_2bit	SRAMEARn1 – first 2-bit error.

Definition at line 166 of file ra8_sram_regs.h.

◆ ra8_sram_ecc_region_off_t

enum ra8_sram_ecc_region_off_t : uint32_t

Per-bank offsets into the SRAM ECC syndrome alias.

Per HUM Ch 58.1 Table 58.1, p 3527: each bank's ECC syndrome bytes live at the bank-specific window listed below. Direct access is only meaningful when SRAMCRn.TSTBYP=1; otherwise the ECC engine intercepts the access and the read/write is invalid.

Enumerator
k_ra8_sram_ecc_bank0_off	SRAM0 ECC region @ 0x221A_0000.
k_ra8_sram_ecc_bank1_off	SRAM1 ECC region @ 0x221B_0000.
k_ra8_sram_ecc_bank2_off	SRAM2 ECC region @ 0x221C_0000.
k_ra8_sram_ecc_bank3_off	SRAM3 ECC region @ 0x221D_0000.
k_ra8_sram_ecc_bank012_sz	64 KB ECC syndrome region.
k_ra8_sram_ecc_bank3_sz	16 KB ECC syndrome region for B3.

Definition at line 131 of file ra8_sram_regs.h.

◆ ra8_sram_ecc_word_t

enum ra8_sram_ecc_word_t : uint8_t

Granularity of ECC-protected SRAM accesses.

Per HUM Ch 58.3.2 "Correction of ECC Errors", p 3538: ECC syndrome is computed per 64-bit word. Initial-fill writes must be 8-byte aligned and 64 bits wide so the syndrome lines up correctly. Per HUM Ch 58.4.2 "Notes on Using Error Checking of SRAM", p 3541: the SRAM is read in 8-byte units, so the safe zero-init stride is 8.

Enumerator
k_ra8_sram_ecc_word_bytes	64-bit ECC word width (bytes).
k_ra8_sram_ecc_word_shift	log2(word bytes), for size>>shift loops.

Definition at line 183 of file ra8_sram_regs.h.

◆ ra8_sram_eccrgn_value_t

enum ra8_sram_eccrgn_value_t : uint8_t

SRAMECCRGNn.ECCRGN field encodings.

Per HUM Ch 58.2.8..58.2.11, p 3533-3535. For SRAM0..SRAM2 the granularity is 128 KB (1=128, 2=256, 3=384, 4=512). SRAM3 is the 128 KB bank so only 0 and 1 are legal there.

Enumerator
k_ra8_sram_eccrgn_off	000b – no ECC target region.
k_ra8_sram_eccrgn_128kb	001b – first 128 KB of bank.
k_ra8_sram_eccrgn_256kb	010b – first 256 KB of bank.
k_ra8_sram_eccrgn_384kb	011b – first 384 KB of bank.
k_ra8_sram_eccrgn_512kb	100b – whole 512 KB bank.
k_ra8_sram_eccrgn_field_msk	ECCRGN[2:0] bit mask.

Definition at line 352 of file ra8_sram_regs.h.

◆ ra8_sram_esar_bit_t

enum ra8_sram_esar_bit_t : uint32_t

SRAMESAR bit positions.

Per HUM Ch 58.2.3 "SRAMESAR : SRAM ECC region Security Attribute Register", p 3529. Only bit 0 (SRAMESA) is defined.

Enumerator
k_ra8_sram_esar_bit_esa	SRAMESA – ECC region Non-Secure.
k_ra8_sram_esar_writable	Union of defined bits.

Definition at line 424 of file ra8_sram_regs.h.

◆ ra8_sram_esr_bit_t

enum ra8_sram_esr_bit_t : uint16_t

SRAMESR / SRAMESCLR bit positions for each bank.

Per HUM Ch 58.2.12 "SRAMESR : SRAM Error Status Register", p 3535 and HUM Ch 58.2.13 "SRAMESCLR", p 3536. Pattern is ERR{n}{0|1} / CLR{n}{0|1} where 0=1-bit and 1=2-bit.

The SRAMESCLR layout is bit-for-bit identical so the same shifts are reused for both registers.

Enumerator
k_ra8_sram_err_bank0_1bit	ERR00 – SRAM0 1-bit.
k_ra8_sram_err_bank0_2bit	ERR01 – SRAM0 2-bit.
k_ra8_sram_err_bank1_1bit	ERR10 – SRAM1 1-bit.
k_ra8_sram_err_bank1_2bit	ERR11 – SRAM1 2-bit.
k_ra8_sram_err_bank2_1bit	ERR20 – SRAM2 1-bit.
k_ra8_sram_err_bank2_2bit	ERR21 – SRAM2 2-bit.
k_ra8_sram_err_bank3_1bit	ERR30 – SRAM3 1-bit.
k_ra8_sram_err_bank3_2bit	ERR31 – SRAM3 2-bit.
k_ra8_sram_err_all_mask	Union of all 8 error bits.
k_ra8_sram_err_all_1bit	Union of all 4 1-bit flags.
k_ra8_sram_err_all_2bit	Union of all 4 2-bit flags.

Definition at line 378 of file ra8_sram_regs.h.

◆ ra8_sram_fill_pattern_t

enum ra8_sram_fill_pattern_t : uint64_t

Fill word for the deterministic zero-init pass.

Per HUM Ch 58.3.2, p 3538: any 64-bit pattern produces a valid syndrome when written under ECC-no-check. Zero is chosen because it matches the post-reset state of every bank's user-visible store and is the cheapest immediate to encode.

Enumerator
k_ra8_sram_zero_init_word	Default fill pattern.

Definition at line 198 of file ra8_sram_regs.h.

◆ ra8_sram_iclk_threshold_t

enum ra8_sram_iclk_threshold_t : uint32_t

ICLK frequency thresholds where SRAMWTSC.WTEN must flip to 1.

Per HUM Ch 58.3.7 "Wait State", p 3540:

250 MHz max ICLK -> 1 wait when ICLK > 125 MHz.
200 MHz max ICLK -> 1 wait when ICLK > 100 MHz.
150 MHz max ICLK -> 1 wait when ICLK > 75 MHz.

The driver multiplies the configured maximum by 2 to get the threshold; these values are kept here for documentation and unit tests that exercise the auto-wait helper.

Enumerator
k_ra8_sram_iclk_threshold_250mhz	250 MHz max -> 125 MHz threshold.
k_ra8_sram_iclk_threshold_200mhz	200 MHz max -> 100 MHz threshold.
k_ra8_sram_iclk_threshold_150mhz	150 MHz max -> 75 MHz threshold.
k_ra8_sram_iclk_max_default	Default RA8D2 max ICLK = 250 MHz.

Definition at line 259 of file ra8_sram_regs.h.

◆ ra8_sram_indexed_t

enum ra8_sram_indexed_t : uint8_t

Stride / base offsets for sparse SRAMCR / SRAMECCRGN slots.

Enumerator
k_ra8_sram_cr_base_off	SRAMCR0 byte offset.
k_ra8_sram_eccrgn_base_off	SRAMECCRGN0 byte offset.
k_ra8_sram_sparse_stride	Stride between sparse slots.

Definition at line 474 of file ra8_sram_regs.h.

◆ ra8_sram_pad_t

enum ra8_sram_pad_t : uint16_t

Reserved-byte gap sizes used inside the SRAM control register block and CPSCU window.

Names every padding gap so the struct definitions do not depend on raw integer literals. Cross-checked against HUM Ch 58.2.

Enumerator
k_ra8_sram_pad_wtsc_to_cr	+0x09..+0x0F gap (bytes).
k_ra8_sram_pad_cr_sparse_bytes	+0x14..+0x1F sparse SRAMCRn.
k_ra8_sram_pad_eccrgn_sparse	+0x34..+0x3F sparse RGNn.
k_ra8_sram_cpscu_pad_sramsar	+0x014..+0x3FF gap (bytes).
k_ra8_sram_cpscu_pad_after_sabar	+0x410..+0x50F gap (bytes).

Definition at line 462 of file ra8_sram_regs.h.

◆ ra8_sram_prcr_key_t

enum ra8_sram_prcr_key_t : uint16_t

SRAMPRCR_S/NS half-word values for unlock / lock.

Per HUM Ch 58.2.4 "SRAMPRCR_S : SRAM Protection Control Register for Secure", p 3530, the upper 8 bits KW[7:0] must be 0xA5 for the PR write-enable bit to take effect. 0xA501 enables subsequent writes to SRAMWTSC / SRAMCRn / SRAMECCRGNn; 0xA500 locks them again.

Enumerator
k_ra8_sram_prcr_unlock	KW=0xA5, PR=1 – writes enabled.
k_ra8_sram_prcr_lock	KW=0xA5, PR=0 – writes blocked.
k_ra8_sram_prcr_kw	KW field bits (15:8).
k_ra8_sram_prcr_pr_msk	PR write-enable bit.

Definition at line 218 of file ra8_sram_regs.h.

◆ ra8_sram_sabar_limit_t

enum ra8_sram_sabar_limit_t : uint32_t

Boundary-address limits per bank for SRAMSABARn.

Per HUM Ch 58.2.1 "SRAMSABARn", p 3527-3528. Each value is the absolute Secure offset where the bank ends – writing a boundary larger than this saturates the whole bank to "Secure". The b12..b0 bits of the boundary must be zero (4 KB granularity).

Enumerator
k_ra8_sram_sabar_align_mask	b12..b0 must be 0.
k_ra8_sram_sabar_field_mask	b20..b13 are the SA boundary.
k_ra8_sram_sabar_bank0_full	Whole SRAM0 Secure.
k_ra8_sram_sabar_bank1_full	Whole SRAM1 Secure.
k_ra8_sram_sabar_bank2_full	Whole SRAM2 Secure.
k_ra8_sram_sabar_bank3_full	Whole SRAM3 Secure.

Definition at line 439 of file ra8_sram_regs.h.

◆ ra8_sram_sar_bit_t

enum ra8_sram_sar_bit_t : uint32_t

SRAMSAR bit positions.

Per HUM Ch 58.2.2 "SRAMSAR : SRAM Security Attribution Register", p 3528. Bits 0..3 cover SRAM0..SRAM3 register security; bit 8 covers SRAMWTSC security.

Enumerator
k_ra8_sram_sar_bit_sa0	SRAM0 register set Non-Secure.
k_ra8_sram_sar_bit_sa1	SRAM1 register set Non-Secure.
k_ra8_sram_sar_bit_sa2	SRAM2 register set Non-Secure.
k_ra8_sram_sar_bit_sa3	SRAM3 register set Non-Secure.
k_ra8_sram_sar_bit_wtsa	SRAMWTSC Non-Secure.
k_ra8_sram_sar_bank_msk	SRAMSA0..SRAMSA3 union.
k_ra8_sram_sar_writable	Union of all defined bits.

Definition at line 406 of file ra8_sram_regs.h.

◆ ra8_sram_wtsc_mask_t

enum ra8_sram_wtsc_mask_t : uint8_t

SRAMWTSC bit masks.

Per HUM Ch 58.2.6 "SRAMWTSC : SRAM Wait State Control Register", p 3531. WTEN=1 inserts one wait state into SRAM read access cycles and is required when ICLK > half the maximum frequency.

Enumerator
k_ra8_sram_wtsc_wten	Insert one wait state on SRAM access.
k_ra8_sram_wtsc_msk	All R/W bits in SRAMWTSC.

Definition at line 239 of file ra8_sram_regs.h.

Function Documentation

◆ ra8_sram_bank_data_ptr()

volatile uint64_t * ra8_sram_bank_data_ptr ( uint8_t bank )

inlinestatic

Per-bank data window helper: pointer to the start of the data alias.

Parameters

[in] bank Bank index 0..3 (caller must validate).

Returns: Volatile pointer to the bank's first 64-bit word.

Per HUM Ch 58.1 Table 58.1, p 3527. SRAM0 starts at the data base, subsequent banks step in 0x80000-byte increments (SRAM3 reuses the same step but only owns the first 0x20000 bytes of its slot).

Definition at line 629 of file ra8_sram_regs.h.

References k_ra8_sram_bank012_size, and k_ra8_sram_data_base_addr.

Referenced by internal_zero_fill_bank(), and ra8_sram_self_test().

◆ ra8_sram_bank_ecc_size_bytes()

uint32_t ra8_sram_bank_ecc_size_bytes ( uint8_t bank )

inlinestatic

Per-bank ECC syndrome region size in bytes.

Parameters

[in] bank Bank index 0..3.

Returns: Number of bytes in the bank's ECC syndrome window (only meaningful when SRAMCRn.TSTBYP=1).

See implementation.

Return values

k_ra8_ok Operation succeeded.

Precondition: Module state is consistent.; Module state is consistent.

Postcondition: Caller-visible state matches the documented contract.; Caller-visible state matches the documented contract.

Note: Not thread-safe unless documented otherwise.

Since: 0.1.0

Definition at line 669 of file ra8_sram_regs.h.

References k_ra8_sram_ecc_bank012_sz, and k_ra8_sram_ecc_bank3_sz.

Referenced by ra8_sram_get_bank_info().

◆ ra8_sram_bank_size_bytes()

uint32_t ra8_sram_bank_size_bytes ( uint8_t bank )

inlinestatic

Per-bank data-region size in bytes.

Parameters

[in] bank Bank index 0..3.

Returns: Number of bytes in the bank's user-visible data window.

See implementation.

Return values

k_ra8_ok Operation succeeded.

Precondition: Module state is consistent.; Module state is consistent.

Postcondition: Caller-visible state matches the documented contract.; Caller-visible state matches the documented contract.

Note: Not thread-safe unless documented otherwise.

Since: 0.1.0

Definition at line 649 of file ra8_sram_regs.h.

References k_ra8_sram_bank012_size, and k_ra8_sram_bank3_size.

Referenced by internal_zero_fill_bank(), ra8_sram_get_bank_info(), and ra8_sram_self_test().

◆ ra8_sram_cpscu_regs()

volatile r_sram_cpscu_regs_t * ra8_sram_cpscu_regs ( void )

inlinestatic

Get pointer to the (Secure) CPSCU SRAM security register block.

Returns: Volatile pointer to the CPSCU SRAM window at 0x40008000.

The CPSCU window is shared with other modules (SRAM is one of several security-attribution clients). This accessor only exposes the SRAM-related slice; do not dereference it for non-SRAM registers.

Definition at line 581 of file ra8_sram_regs.h.

References k_ra8_sram_cpscu_base_addr.

Referenced by internal_apply_security(), ra8_sram_set_boundary(), ra8_sram_set_ecc_security(), and ra8_sram_set_security().

◆ ra8_sram_cr_ptr()

volatile uint8_t * ra8_sram_cr_ptr	(	volatile r_sram_regs_t *	regs,
		uint8_t	bank )

inlinestatic

Indexed write helper: SRAMCRn slot.

Parameters

[in]	regs	Result of ra8_sram_regs().
[in]	bank	Bank index 0..3 (caller must validate).

Returns: Pointer to the per-bank SRAMCRn 8-bit slot.

The HUM lays out SRAMCR0..3 with a 4-byte stride, so the SRAMCR member of r_sram_regs_t cannot be a packed uint8_t[4]. This helper hides the cast and stride math.

Definition at line 597 of file ra8_sram_regs.h.

References k_ra8_sram_cr_base_off, and k_ra8_sram_sparse_stride.

Referenced by internal_write_cr_locked().

◆ ra8_sram_eccrgn_ptr()

volatile uint8_t * ra8_sram_eccrgn_ptr	(	volatile r_sram_regs_t *	regs,
		uint8_t	bank )

inlinestatic

Indexed write helper: SRAMECCRGNn slot.

Parameters

[in]	regs	Result of ra8_sram_regs().
[in]	bank	Bank index 0..3 (caller must validate).

Returns: Pointer to the per-bank SRAMECCRGNn 8-bit slot.

Definition at line 611 of file ra8_sram_regs.h.

References k_ra8_sram_eccrgn_base_off, and k_ra8_sram_sparse_stride.

Referenced by internal_write_eccrgn_locked().

◆ ra8_sram_regs()

volatile r_sram_regs_t * ra8_sram_regs ( void )

inlinestatic

Get pointer to the (Secure) SRAM control register block.

Returns: Volatile pointer to the SRAM control window at 0x40002000.

On the bare-metal target this is real MMIO. Under RA8_OFF_TARGET the same address is backed by host RAM via tests/mocks/src/ra8_fake_mmap.c, so the same accessor works on host tests without a separate mock header.

Definition at line 566 of file ra8_sram_regs.h.

References k_ra8_sram_base_addr.

Referenced by internal_write_cr_locked(), internal_write_eccrgn_locked(), internal_write_wtsc_locked(), ra8_sram_clear_address(), ra8_sram_clear_status(), ra8_sram_get_status(), ra8_sram_init(), and ra8_sram_self_test().

Data Structures

Enumerations

Functions

Detailed Description

Enumeration Type Documentation

◆ ra8_sram_addr_t

◆ ra8_sram_bank_count_t

◆ ra8_sram_bank_offset_t

◆ ra8_sram_cr_bit_t

◆ ra8_sram_cr_eccmod_t

◆ ra8_sram_cr_mask_t

◆ ra8_sram_cr_self_test_t

◆ ra8_sram_ear_pair_t

◆ ra8_sram_ecc_region_off_t

◆ ra8_sram_ecc_word_t

◆ ra8_sram_eccrgn_value_t

◆ ra8_sram_esar_bit_t

◆ ra8_sram_esr_bit_t

◆ ra8_sram_fill_pattern_t

◆ ra8_sram_iclk_threshold_t

◆ ra8_sram_indexed_t

◆ ra8_sram_pad_t

◆ ra8_sram_prcr_key_t

◆ ra8_sram_sabar_limit_t

◆ ra8_sram_sar_bit_t

◆ ra8_sram_wtsc_mask_t

Function Documentation

◆ ra8_sram_bank_data_ptr()

◆ ra8_sram_bank_ecc_size_bytes()

◆ ra8_sram_bank_size_bytes()

◆ ra8_sram_cpscu_regs()

◆ ra8_sram_cr_ptr()

◆ ra8_sram_eccrgn_ptr()

◆ ra8_sram_regs()