ra8_sram_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stddef.h>
#include <stdint.h>
 
/* =============================================================================
 * Base addresses
 * =============================================================================
 */

typedef enum : uintptr_t {
  k_ra8_sram_base_addr       = 0x40002000UL, 
  k_ra8_sram_base_addr_ns    = 0x50002000UL, 
  k_ra8_sram_cpscu_base_addr = 0x40008000UL, 
  k_ra8_sram_cpscu_base_ns   = 0x50008000UL, 
  k_ra8_sram_data_base_addr  = 0x22000000UL, 
  k_ra8_sram_data_base_ns    = 0x32000000UL, 
} ra8_sram_addr_t;

typedef enum : uint32_t {
  k_ra8_sram_bank0_data_off = 0x00000000UL, 
  k_ra8_sram_bank1_data_off = 0x00080000UL, 
  k_ra8_sram_bank2_data_off = 0x00100000UL, 
  k_ra8_sram_bank3_data_off = 0x00180000UL, 
  k_ra8_sram_bank012_size   = 0x00080000UL, 
  k_ra8_sram_bank3_size     = 0x00020000UL, 
} ra8_sram_bank_offset_t;

typedef enum : uint32_t {
  k_ra8_sram_ecc_bank0_off  = 0x001A0000UL, 
  k_ra8_sram_ecc_bank1_off  = 0x001B0000UL, 
  k_ra8_sram_ecc_bank2_off  = 0x001C0000UL, 
  k_ra8_sram_ecc_bank3_off  = 0x001D0000UL, 
  k_ra8_sram_ecc_bank012_sz = 0x00010000UL, 
  k_ra8_sram_ecc_bank3_sz   = 0x00004000UL, 
} ra8_sram_ecc_region_off_t;
 
/* =============================================================================
 * Bank / layout constants
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sram_bank_count = 4U, 
} ra8_sram_bank_count_t;

typedef enum : uint8_t {
  k_ra8_sram_ear_pair_count = 2U, 
  k_ra8_sram_ear_slot_1bit  = 0U, 
  k_ra8_sram_ear_slot_2bit  = 1U, 
} ra8_sram_ear_pair_t;

typedef enum : uint8_t {
  k_ra8_sram_ecc_word_bytes = 8U, 
  k_ra8_sram_ecc_word_shift = 3U, 
} ra8_sram_ecc_word_t;

typedef enum : uint64_t {
  k_ra8_sram_zero_init_word = 0x0000000000000000ULL, 
} ra8_sram_fill_pattern_t;
 
/* =============================================================================
 * SRAMPRCR -- write-protect key
 * =============================================================================
 */

typedef enum : uint16_t {
  k_ra8_sram_prcr_unlock = 0xA501U, 
  k_ra8_sram_prcr_lock   = 0xA500U, 
  k_ra8_sram_prcr_kw     = 0xA500U, 
  k_ra8_sram_prcr_pr_msk = 0x0001U, 
} ra8_sram_prcr_key_t;
 
/* =============================================================================
 * SRAMWTSC -- wait-state enable
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sram_wtsc_wten = 0x01U, 
  k_ra8_sram_wtsc_msk  = 0x01U, 
} ra8_sram_wtsc_mask_t;

typedef enum : uint32_t {
  k_ra8_sram_iclk_threshold_250mhz = 125000000UL, 
  k_ra8_sram_iclk_threshold_200mhz = 100000000UL, 
  k_ra8_sram_iclk_threshold_150mhz = 75000000UL,  
  k_ra8_sram_iclk_max_default      = 250000000UL, 
} ra8_sram_iclk_threshold_t;
 
/* =============================================================================
 * SRAMCRn -- ECC mode + OAD + E1STSEN + TSTBYP
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sram_cr_bit_oad     = 0U, 
  k_ra8_sram_cr_bit_eccmod0 = 2U, 
  k_ra8_sram_cr_bit_eccmod1 = 3U, 
  k_ra8_sram_cr_bit_e1stsen = 4U, 
  k_ra8_sram_cr_bit_tstbyp  = 7U, 
} ra8_sram_cr_bit_t;

typedef enum : uint8_t {
  k_ra8_sram_cr_mask_oad     = 0x01U, 
  k_ra8_sram_cr_mask_eccmod  = 0x0CU, 
  k_ra8_sram_cr_mask_e1stsen = 0x10U, 
  k_ra8_sram_cr_mask_tstbyp  = 0x80U, 
  k_ra8_sram_cr_mask_all     = 0x9DU, 
} ra8_sram_cr_mask_t;

typedef enum : uint8_t {
  k_ra8_sram_eccmod_disabled = 0x00U, 
  k_ra8_sram_eccmod_no_check = 0x08U, 
  k_ra8_sram_eccmod_with_chk = 0x0CU, 
} ra8_sram_cr_eccmod_t;

typedef enum : uint8_t {
  k_ra8_sram_cr_self_test_phase_write  = 0x08U, 
  k_ra8_sram_cr_self_test_phase_bypass = 0x80U, 
  k_ra8_sram_cr_self_test_phase_verify = 0x1CU, 
} ra8_sram_cr_self_test_t;
 
/* =============================================================================
 * SRAMECCRGNn -- ECC region size
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sram_eccrgn_off       = 0U,    
  k_ra8_sram_eccrgn_128kb     = 1U,    
  k_ra8_sram_eccrgn_256kb     = 2U,    
  k_ra8_sram_eccrgn_384kb     = 3U,    
  k_ra8_sram_eccrgn_512kb     = 4U,    
  k_ra8_sram_eccrgn_field_msk = 0x07U, 
} ra8_sram_eccrgn_value_t;
 
/* =============================================================================
 * SRAMESR / SRAMESCLR -- per-bank error / clear bits
 * =============================================================================
 */

typedef enum : uint16_t {
  k_ra8_sram_err_bank0_1bit = 0x0001U, 
  k_ra8_sram_err_bank0_2bit = 0x0002U, 
  k_ra8_sram_err_bank1_1bit = 0x0004U, 
  k_ra8_sram_err_bank1_2bit = 0x0008U, 
  k_ra8_sram_err_bank2_1bit = 0x0010U, 
  k_ra8_sram_err_bank2_2bit = 0x0020U, 
  k_ra8_sram_err_bank3_1bit = 0x0040U, 
  k_ra8_sram_err_bank3_2bit = 0x0080U, 
  k_ra8_sram_err_all_mask   = 0x00FFU, 
  k_ra8_sram_err_all_1bit   = 0x0055U, 
  k_ra8_sram_err_all_2bit   = 0x00AAU, 
} ra8_sram_esr_bit_t;
 
/* =============================================================================
 * CPSCU -- SRAMSAR / SRAMSABARn / SRAMESAR security attribution
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_sram_sar_bit_sa0  = 0x00000001UL, 
  k_ra8_sram_sar_bit_sa1  = 0x00000002UL, 
  k_ra8_sram_sar_bit_sa2  = 0x00000004UL, 
  k_ra8_sram_sar_bit_sa3  = 0x00000008UL, 
  k_ra8_sram_sar_bit_wtsa = 0x00000100UL, 
  k_ra8_sram_sar_bank_msk = 0x0000000FUL, 
  k_ra8_sram_sar_writable = 0x0000010FUL, 
} ra8_sram_sar_bit_t;

typedef enum : uint32_t {
  k_ra8_sram_esar_bit_esa  = 0x00000001UL, 
  k_ra8_sram_esar_writable = 0x00000001UL, 
} ra8_sram_esar_bit_t;

typedef enum : uint32_t {
  k_ra8_sram_sabar_align_mask = 0x00001FFFUL, 
  k_ra8_sram_sabar_field_mask = 0x001FE000UL, 
  k_ra8_sram_sabar_bank0_full = 0x00080000UL, 
  k_ra8_sram_sabar_bank1_full = 0x00100000UL, 
  k_ra8_sram_sabar_bank2_full = 0x00180000UL, 
  k_ra8_sram_sabar_bank3_full = 0x001A0000UL, 
} ra8_sram_sabar_limit_t;
 
/* =============================================================================
 * Register window layout
 * =============================================================================
 */

typedef enum : uint16_t {
  k_ra8_sram_pad_wtsc_to_cr        = 7U,     
  k_ra8_sram_pad_cr_sparse_bytes   = 12U,    
  k_ra8_sram_pad_eccrgn_sparse     = 12U,    
  k_ra8_sram_cpscu_pad_sramsar     = 0x3ECU, 
  k_ra8_sram_cpscu_pad_after_sabar = 0x100U, 
} ra8_sram_pad_t;

typedef enum : uint8_t {
  k_ra8_sram_cr_base_off     = 0x10U, 
  k_ra8_sram_eccrgn_base_off = 0x30U, 
  k_ra8_sram_sparse_stride   = 4U,    
} ra8_sram_indexed_t;

typedef struct {
  volatile uint16_t SRAMPRCR_S;                     
  volatile uint16_t _r0;                            
  volatile uint16_t SRAMPRCR_NS;                    
  volatile uint16_t _r1;                            
  volatile uint8_t  SRAMWTSC;                       
  volatile uint8_t  _r2[k_ra8_sram_pad_wtsc_to_cr]; 
  volatile uint8_t  SRAMCR[k_ra8_sram_bank_count];  
  /* The HUM lays SRAMCRn at +0x10 + 0x04 * n, so we cannot pack them
   * as a contiguous uint8_t array. Model them as one 32-bit word per
   * bank instead -- the public API only writes the low byte. */
  volatile uint8_t
    _r3[k_ra8_sram_pad_cr_sparse_bytes];              
  volatile uint8_t _r4[16];                           
  volatile uint8_t SRAMECCRGN[k_ra8_sram_bank_count]; 
  volatile uint8_t
    _r5[k_ra8_sram_pad_eccrgn_sparse]; 
  volatile uint16_t SRAMESR;           
  volatile uint16_t _r6;               
  volatile uint8_t  _r7[4];            
  volatile uint16_t SRAMESCLR;         
  volatile uint16_t _r8;               
  volatile uint8_t  _r9[4];            
  volatile uint32_t SRAMEAR[k_ra8_sram_bank_count]
                           [k_ra8_sram_ear_pair_count]; 
} r_sram_regs_t;

typedef struct {
  volatile uint8_t  _r0[0x010];                            
  volatile uint32_t SRAMSAR;                               
  volatile uint8_t  _r1[k_ra8_sram_cpscu_pad_sramsar];     
  volatile uint32_t SRAMSABAR[k_ra8_sram_bank_count];      
  volatile uint8_t  _r2[k_ra8_sram_cpscu_pad_after_sabar]; 
  volatile uint32_t SRAMESAR;                              
  volatile uint32_t _r3;                                   
} r_sram_cpscu_regs_t;

static inline volatile r_sram_regs_t* ra8_sram_regs(void)
{
  return (volatile r_sram_regs_t*)k_ra8_sram_base_addr;
}

static inline volatile r_sram_cpscu_regs_t* ra8_sram_cpscu_regs(void)
{
  return (volatile r_sram_cpscu_regs_t*)k_ra8_sram_cpscu_base_addr;
}

static inline volatile uint8_t* ra8_sram_cr_ptr(volatile r_sram_regs_t* regs, uint8_t bank)
{
  /* SRAMCRn at +0x10 + 4 * n. */
  const uintptr_t base = (uintptr_t)regs;
  return (volatile uint8_t*)(base + (uintptr_t)k_ra8_sram_cr_base_off +
                             ((uintptr_t)bank * (uintptr_t)k_ra8_sram_sparse_stride));
}

static inline volatile uint8_t* ra8_sram_eccrgn_ptr(volatile r_sram_regs_t* regs, uint8_t bank)
{
  /* SRAMECCRGNn at +0x30 + 4 * n. */
  const uintptr_t base = (uintptr_t)regs;
  return (volatile uint8_t*)(base + (uintptr_t)k_ra8_sram_eccrgn_base_off +
                             ((uintptr_t)bank * (uintptr_t)k_ra8_sram_sparse_stride));
}

static inline volatile uint64_t* ra8_sram_bank_data_ptr(uint8_t bank)
{
  const uintptr_t base = (uintptr_t)k_ra8_sram_data_base_addr;
  return (volatile uint64_t*)(base + ((uintptr_t)bank * (uintptr_t)k_ra8_sram_bank012_size));
}

static inline uint32_t ra8_sram_bank_size_bytes(uint8_t bank)
{
  return (bank == 3U) ? k_ra8_sram_bank3_size : k_ra8_sram_bank012_size;
}

static inline uint32_t ra8_sram_bank_ecc_size_bytes(uint8_t bank)
{
  return (bank == 3U) ? k_ra8_sram_ecc_bank3_sz : k_ra8_sram_ecc_bank012_sz;
}
 
#ifdef __cplusplus
}
#endif