ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_sram_security.c
Go to the documentation of this file.
1
24
25#include <stdint.h>
26
27#include "ra8_check.h"
28#include "ra8_err.h"
29#include "ra8_log.h"
30#include "ra8_sram.h"
31#include "ra8_sram_internal.h"
32#include "ra8_sram_regs.h"
33
34/* =============================================================================
35 * Constants
36 * =============================================================================
37 */
38
40static const char* s_tag = "SRAM";
41
42/* =============================================================================
43 * Module state
44 * =============================================================================
45 */
46
49
51void* g_sram_on_error_ctx = nullptr;
52
55 nullptr,
56 nullptr,
57 nullptr,
58 nullptr,
59};
60
63 nullptr,
64 nullptr,
65 nullptr,
66 nullptr,
67};
68
69/* =============================================================================
70 * TrustZone security attribution
71 * =============================================================================
72 */
73
74[[nodiscard]] ra8_err_t ra8_sram_set_security(uint32_t sa_mask)
75{
76 if ((sa_mask & ~k_ra8_sram_sar_writable) != 0U) {
78 }
79 volatile r_sram_cpscu_regs_t* cpscu = ra8_sram_cpscu_regs();
80 /* HUM Ch 58.2.2 "SRAMSAR : SRAM Security Attribution Register",
81 * p 3528. */
82 cpscu->SRAMSAR = sa_mask;
83 return k_ra8_ok;
84}
85
86[[nodiscard]] ra8_err_t ra8_sram_set_ecc_security(bool non_secure)
87{
88 volatile r_sram_cpscu_regs_t* cpscu = ra8_sram_cpscu_regs();
89 /* HUM Ch 58.2.3 "SRAMESAR : SRAM ECC region Security Attribute
90 * Register", p 3529. */
91 uint32_t value = 0U;
92 if (non_secure) {
94 }
95 cpscu->SRAMESAR = value;
96 return k_ra8_ok;
97}
98
99[[nodiscard]] ra8_err_t ra8_sram_set_boundary(uint8_t bank, uint32_t offset)
100{
101 if ((uint16_t)bank >= (uint16_t)k_ra8_sram_bank_count) {
103 }
104 if ((offset & k_ra8_sram_sabar_align_mask) != 0U) {
106 }
107 volatile r_sram_cpscu_regs_t* cpscu = ra8_sram_cpscu_regs();
108 /* HUM Ch 58.2.1 "SRAMSABARn : SRAM Security Attribute Boundary
109 * Address Register", p 3527 -- write the absolute Secure offset. */
110 cpscu->SRAMSABAR[bank] = offset;
111 return k_ra8_ok;
112}
113
114/* =============================================================================
115 * Error callback path
116 * =============================================================================
117 */
118
120{
121 RA8_CHECK_NULL_PTR(fn, s_tag, "fn must not be nullptr");
122 g_sram_on_error = fn;
124 return k_ra8_ok;
125}
126
127[[nodiscard]] ra8_err_t
129{
130 RA8_CHECK_NULL_PTR(fn, s_tag, "fn must not be nullptr");
131 if ((uint16_t)bank >= (uint16_t)k_ra8_sram_bank_count) {
133 }
134 g_sram_on_error_bank[bank] = fn;
135 g_sram_on_error_bank_ctx[bank] = ctx;
136 return k_ra8_ok;
137}
138
139void ra8_sram_dispatch(uint8_t bank, bool is_2bit, uintptr_t err_addr)
140{
141 if ((uint16_t)bank >= (uint16_t)k_ra8_sram_bank_count) {
142 return;
143 }
144 const ra8_sram_error_fn_t global_fn = g_sram_on_error;
145 void* const global_ctx = g_sram_on_error_ctx;
146 if (global_fn != nullptr) {
147 global_fn(global_ctx, bank, is_2bit, err_addr);
148 }
149 const ra8_sram_error_fn_t bank_fn = g_sram_on_error_bank[bank];
150 void* const bank_ctx = g_sram_on_error_bank_ctx[bank];
151 if (bank_fn != nullptr) {
152 bank_fn(bank_ctx, bank, is_2bit, err_addr);
153 }
154}
155
157{
158 ra8_sram_status_t local = {};
159 /* HUM Ch 58.2.12 "SRAMESR : SRAM Error Status Register For ECC
160 * RAM" p 3535-3537 -- read SRAMESR + EAR via the helper. */
161 const ra8_err_t err = ra8_sram_get_status(&local);
162 if (err != k_ra8_ok) {
163 return 0U;
164 }
165 if (out_status != nullptr) {
166 *out_status = local;
167 }
168
169 uint16_t fired = 0U;
170 for (uint8_t bank = 0U; bank < k_ra8_sram_bank_count; ++bank) {
171 const uint16_t one_bit_pos = (uint16_t)((uint16_t)2U * (uint16_t)bank);
172 const uint16_t two_bit_pos = (uint16_t)(one_bit_pos + 1U);
173 const uint16_t one_bit_msk = (uint16_t)((uint16_t)1U << one_bit_pos);
174 const uint16_t two_bit_msk = (uint16_t)((uint16_t)1U << two_bit_pos);
175
176 if ((local.raw_esr & one_bit_msk) != 0U) {
177 ra8_sram_dispatch(bank, false, local.addr_1bit[bank]);
178 fired = (uint16_t)(fired | one_bit_msk);
179 }
180 if ((local.raw_esr & two_bit_msk) != 0U) {
181 ra8_sram_dispatch(bank, true, local.addr_2bit[bank]);
182 fired = (uint16_t)(fired | two_bit_msk);
183 }
184 }
185 return fired;
186}
static const char * s_tag
Logging / check tag.
Definition ra8_app.c:17
Validation and Error-Checking Macros for ra8-firmware.
#define RA8_CHECK_NULL_PTR(ptr, tag, message)
Reject nullptr pointer, returning k_ra8_err_null_ptr.
Definition ra8_check.h:243
Error Code Definitions for ra8-firmware.
@ k_ra8_err_invalid_arg
Invalid function argument.
Definition ra8_err.h:152
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
Lightweight Logging Interface for ra8-firmware.
SRAM (with ECC) HAL driver public API.
void(* ra8_sram_error_fn_t)(void *ctx, uint8_t bank, bool is_2bit, uintptr_t err_addr)
ECC error callback signature.
Definition ra8_sram.h:221
ra8_err_t ra8_sram_get_status(ra8_sram_status_t *out)
Snapshot the current ECC error state across all four banks.
Definition ra8_sram.c:682
src/-local shared surface for the SRAM HAL driver split.
ra8_sram_error_fn_t g_sram_on_error
Registered global ECC error callback (NULL until attach).
ra8_sram_error_fn_t g_sram_on_error_bank[k_ra8_sram_bank_count]
Per-bank ECC error callback table (NULL until attach).
void * g_sram_on_error_ctx
Caller context forwarded to g_sram_on_error.
void * g_sram_on_error_bank_ctx[k_ra8_sram_bank_count]
Per-bank context forwarded to g_sram_on_error_bank.
SRAM (with ECC) control / status / security register layout.
@ k_ra8_sram_sabar_align_mask
b12..b0 must be 0.
static volatile r_sram_cpscu_regs_t * ra8_sram_cpscu_regs(void)
Get pointer to the (Secure) CPSCU SRAM security register block.
@ k_ra8_sram_esar_bit_esa
SRAMESA – ECC region Non-Secure.
@ k_ra8_sram_sar_writable
Union of all defined bits.
@ k_ra8_sram_bank_count
SRAM0, SRAM1, SRAM2, SRAM3.
ra8_err_t ra8_sram_attach_bank_handler(uint8_t bank, ra8_sram_error_fn_t fn, void *ctx)
Attach a per-bank ECC error callback.
ra8_err_t ra8_sram_set_boundary(uint8_t bank, uint32_t offset)
Write SRAMSABARn (per-bank Secure/Non-Secure boundary).
void ra8_sram_dispatch(uint8_t bank, bool is_2bit, uintptr_t err_addr)
Dispatch an ECC error event to the registered handler.
ra8_err_t ra8_sram_attach_handler(ra8_sram_error_fn_t fn, void *ctx)
Attach the global ECC error callback.
ra8_err_t ra8_sram_set_ecc_security(bool non_secure)
Write SRAMESAR (ECC region security).
uint16_t ra8_sram_dispatch_from_esr(ra8_sram_status_t *out_status)
Read SRAMESR + EAR and dispatch every latched flag.
ra8_err_t ra8_sram_set_security(uint32_t sa_mask)
Write SRAMSAR (per-bank register security + WTSC security).
Memory layout of the CPSCU SRAM security window.
volatile uint32_t SRAMSAR
+0x010 SRAM register security.
volatile uint32_t SRAMSABAR[k_ra8_sram_bank_count]
+0x400..+0x40F Bank boundary.
volatile uint32_t SRAMESAR
+0x510 ECC region security.
Snapshot of ECC error state (filled by ra8_sram_get_status).
Definition ra8_sram.h:189
uintptr_t addr_2bit[k_ra8_sram_bank_count]
Captured 2-bit error address per bank.
Definition ra8_sram.h:194
uintptr_t addr_1bit[k_ra8_sram_bank_count]
Captured 1-bit error address per bank.
Definition ra8_sram.h:193
uint16_t raw_esr
Raw SRAMESR value.
Definition ra8_sram.h:190