General PWM Timer (GPT) driver implementation. More...

#include "ra8_gpt.h"
#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_dma.h"
#include "ra8_dmac.h"
#include "ra8_err.h"
#include "ra8_gpt_capture.h"
#include "ra8_gpt_regs.h"
#include "ra8_log.h"
#include "ra8_mstp.h"

Include dependency graph for ra8_gpt.c:

Data Structures
struct	ra8_gpt_state_t
	Per-channel runtime state (callback, configured flag). More...
struct	ra8_gpt_three_phase_state_t
	Driver-internal three-phase tracking state. More...

Enumerations
enum	ra8_gtwp_t : uint32_t { k_ra8_gtwp_key_unlock = 0xA500U , k_ra8_gtwp_key_lock = 0xA501U }
	GTWP write-protect key. More...
enum	ra8_gptclkcr_bits_t : uint32_t { k_ra8_gptclkcr_bpen = 0x00000001UL }
	GTCLKCR block-level clock-control bits. More...
enum	ra8_gpt_bits_t : uint32_t { k_ra8_gpt_gtcr_cst_set = 0x00000001UL , k_ra8_gpt_gtcr_md_shift = 16U , k_ra8_gpt_gtcr_tpcs_shift = 23U , k_ra8_gpt_gtstr_start = 0x00000001UL , k_ra8_gpt_gtstp_stop = 0x00000001UL , k_ra8_gpt_gtst_mask = 0x000000C3UL }
	GTCR / GTSTR / GTSTP / GTST bit positions. More...
enum	ra8_gpt_gtior_bits_t : uint32_t { k_ra8_gpt_gtioa_mask = 0x0000001FUL , k_ra8_gpt_gtioa_shift = 0U , k_ra8_gpt_oadflt_mask = 0x00000040UL , k_ra8_gpt_oadflt_shift = 6U , k_ra8_gpt_oae_mask = 0x00000100UL , k_ra8_gpt_oadf_mask = 0x00000600UL , k_ra8_gpt_oadf_shift = 9U , k_ra8_gpt_gtiob_mask = 0x001F0000UL , k_ra8_gpt_gtiob_shift = 16U , k_ra8_gpt_obdflt_mask = 0x00400000UL , k_ra8_gpt_obdflt_shift = 22U , k_ra8_gpt_obe_mask = 0x01000000UL , k_ra8_gpt_obdf_mask = 0x06000000UL , k_ra8_gpt_obdf_shift = 25U , k_ra8_gpt_gtio_active_high = 0x9UL , k_ra8_gpt_gtio_active_low = 0x6UL }
	GTIOR field positions and masks. More...
enum	ra8_gpt_buffer_bits_t : uint32_t { k_ra8_gpt_gtber_ccra_single = 0x00010000UL , k_ra8_gpt_gtber_ccrb_single = 0x00040000UL , k_ra8_gpt_gtdtcr_tde = 0x00000001UL , k_ra8_gpt_gtcr_cst_mask = 0x00000001UL }
	GTBER bits and GTDTCR bits used by the runtime PWM API. More...
enum	ra8_gpt_ccr_idx_t : uint8_t { k_ra8_gpt_ccr_idx_a = 0U , k_ra8_gpt_ccr_idx_b = 1U , k_ra8_gpt_ccr_idx_c = 2U , k_ra8_gpt_ccr_idx_e = 3U }
	Index positions inside GTCCR[6] used by the buffer-based duty cycle setter. More...

Functions
static void	internal_gpt_clock_block_init (void)
	Block-level GPT clock-control init (one-shot, MSTP-stopped).
static uint32_t	internal_gtcr (ra8_gpt_mode_t mode, ra8_gpt_prescaler_t ps)
ra8_err_t	ra8_gpt_start_free_run (uint8_t channel, uint32_t period)
	Configure a GPT channel as a free-running up-counter.
ra8_err_t	ra8_gpt_stop (uint8_t channel)
	Stop a GPT channel.
ra8_err_t	ra8_gpt_read (uint8_t channel, uint32_t *out)
	Read the current counter value.
ra8_err_t	ra8_gpt_init (uint8_t channel, const ra8_gpt_cfg_t *cfg)
	Initialise a GPT channel with a full config descriptor.
ra8_err_t	ra8_gpt_deinit (uint8_t channel)
	Tear down a channel (stop + MSTP release).
ra8_err_t	ra8_gpt_set_period (uint8_t channel, uint32_t period)
	Change the GPT period (GTPR / GTPBR) at runtime.
ra8_err_t	ra8_gpt_set_duty (uint8_t channel, ra8_gpt_ccr_sel_t which, uint32_t value)
	Change one compare register (GTCCRA / GTCCRB) at runtime.
ra8_err_t	ra8_gpt_get_status (uint8_t channel, uint32_t *out_mask)
	Read GTST overflow / underflow / compare flags.
ra8_err_t	ra8_gpt_clear_status (uint8_t channel, uint32_t mask)
	Clear GTST flag bits (write-0 to clear).
ra8_err_t	ra8_gpt_attach_handler (uint8_t channel, ra8_gpt_event_fn_t fn, void *ctx)
	Attach a GPT event callback for a channel.
ra8_err_t	ra8_gpt_enter_stop (uint8_t channel)
	Put a channel into MSTP-gated stop.
ra8_err_t	ra8_gpt_exit_stop (uint8_t channel)
	Exit MSTP-gated stop.
ra8_err_t	ra8_gpt_write_dma (uint8_t channel, const uint32_t periods, uint16_t count, ra8_dma_complete_fn_t on_complete, void ctx, uint8_t *out_dma_channel)
	Stream a buffer of period values into GPT GTPR via DMA.
ra8_err_t	ra8_gpt_read_dma (uint8_t channel, uint32_t out_counts, uint16_t count, ra8_dma_complete_fn_t on_complete, void ctx, uint8_t *out_dma_channel)
	Capture a stream of GTCNT values into a buffer via DMA.
ra8_err_t	ra8_gpt_capture_configure (uint8_t channel, ra8_gpt_ccr_sel_t which, uint32_t source_mask)
	Arm a GPT channel for input capture on GTCCRA or GTCCRB.
ra8_err_t	ra8_gpt_capture_read (uint8_t channel, ra8_gpt_ccr_sel_t which, uint32_t *out_value)
	Read the value latched by the last input capture.
ra8_err_t	ra8_gpt_event_count_configure (uint8_t channel, uint32_t up_source, uint32_t down_source)
	Configure external event (edge) counting on GTCNT.
ra8_err_t	ra8_gpt_period_set (uint8_t channel, uint32_t period_counts)
	Update the GPT period via the shadow buffer (GTPBR).
ra8_err_t	ra8_gpt_duty_cycle_set (uint8_t channel, ra8_gpt_pwm_pin_t pin, uint32_t compare_counts)
	Update one PWM compare value via the shadow buffer.
ra8_err_t	ra8_gpt_counter_set (uint8_t channel, uint32_t value)
	Force GTCNT to value (timer must be stopped).
static uint32_t	internal_gtio_pattern (ra8_gpt_pwm_polarity_t polarity)
	Build the GTIO[A/B] sub-field encoding for the requested polarity.
ra8_err_t	ra8_gpt_pwm_pin_configure (uint8_t channel, ra8_gpt_pwm_pin_t pin, const ra8_gpt_pwm_pin_cfg_t *cfg)
	Configure GTIOR for one PWM output pin.
ra8_err_t	ra8_gpt_dead_time_set (uint8_t channel, uint32_t rising_dt, uint32_t falling_dt)
	Programme the dead-time value pair for complementary PWM.
static ra8_err_t	internal_three_phase_init_subs (const ra8_gpt_three_phase_cfg_t cfg, uint32_t out_mask)
	Bring up the three GPT submodules and build the start mask.
ra8_err_t	ra8_gpt_three_phase_open (const ra8_gpt_three_phase_cfg_t *cfg)
	Open three GPT channels as a phase-synchronized U/V/W triple.
ra8_err_t	ra8_gpt_three_phase_set_duty (uint32_t u_duty, uint32_t v_duty, uint32_t w_duty)
	Atomically update U/V/W compare values via the shadow buffer.
ra8_err_t	ra8_gpt_three_phase_close (void)
	Stop and tear down the three U/V/W channels.
static void	internal_dispatch (uint8_t channel, uint32_t status_mask)
void	ra8_gpt_dispatch_ovf (uint8_t channel)
	Dispatch GPT overflow (GTCIV) – clear + fire callback.
void	ra8_gpt_dispatch_und (uint8_t channel)
	Dispatch GPT underflow (GTCIU) – clear + fire callback.
void	ra8_gpt_dispatch_ccra (uint8_t channel)
	Dispatch GPT compare-match A (GTCIA) – clear + fire callback.
void	ra8_gpt_dispatch_ccrb (uint8_t channel)
	Dispatch GPT compare-match B (GTCIB) – clear + fire callback.

Variables
static const char *	s_tag = "GPT"
static const ra8_mstp_t	s_gpt_mstp_table [k_ra8_gpt_channel_count]
	Channel-index -> MSTP id lookup.
static ra8_gpt_state_t	s_gpt_state [k_ra8_gpt_channel_count]
static ra8_gpt_three_phase_state_t	s_three_phase

Detailed Description

General PWM Timer (GPT) driver implementation.

Provides a minimal "free-running 32-bit timer" interface on top of the GPT register block. A full PWM / compare-match driver will land once the motor-control layer needs it.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_gpt.c.

Enumeration Type Documentation

◆ ra8_gpt_bits_t

enum ra8_gpt_bits_t : uint32_t

GTCR / GTSTR / GTSTP / GTST bit positions.

Per HUM Ch 22.2.5 "GTCR : General PWM Timer Control Register", p 904..906: CST = bit 0, MD = bits 16..19, TPCS = bits 23..26. GTST flag layout from HUM Ch 22.2.16 "GTST : General PWM Timer Status Register", p 962..964: TCFA = bit 0, TCFB = bit 1, TCFPO = bit 6, TCFPU = bit 7.

Enumerator
k_ra8_gpt_gtcr_cst_set	GTCR.CST start.
k_ra8_gpt_gtcr_md_shift	GTCR.MD bit0.
k_ra8_gpt_gtcr_tpcs_shift	GTCR.TPCS bit0.
k_ra8_gpt_gtstr_start	GTSTR.CSTRT0 write.
k_ra8_gpt_gtstp_stop	GTSTP.CSTOP0 write.
k_ra8_gpt_gtst_mask	TCFPU\|TCFPO\|TCFB\|TCFA.

Definition at line 140 of file ra8_gpt.c.

◆ ra8_gpt_buffer_bits_t

enum ra8_gpt_buffer_bits_t : uint32_t

GTBER bits and GTDTCR bits used by the runtime PWM API.

GTBER layout from RA8D2 CMSIS R_GPT0_GTBER (HUM Ch 22.2.17, p 932..935): CCRA at bits 16..17, CCRB at bits 18..19. Setting the lower bit of each pair to 1 selects single-buffer (GTCCRC -> GTCCRA / GTCCRE -> GTCCRB) reload at cycle end.

GTDTCR.TDE is bit 0 (HUM Ch 22.2.27 "GTDTCR", p 941..942).

The compare_c / compare_e indices are GTCCR[2] and GTCCR[3] respectively per HUM Ch 22.2.20.

Enumerator
k_ra8_gpt_gtber_ccra_single	RA8 GPT gtber ccra single.
k_ra8_gpt_gtber_ccrb_single	RA8 GPT gtber ccrb single.
k_ra8_gpt_gtdtcr_tde	RA8 GPT gtdtcr tde.
k_ra8_gpt_gtcr_cst_mask	RA8 GPT gtcr cst mask.

Definition at line 207 of file ra8_gpt.c.

◆ ra8_gpt_ccr_idx_t

enum ra8_gpt_ccr_idx_t : uint8_t

Index positions inside GTCCR[6] used by the buffer-based duty cycle setter.

Mirrors FSP GPT_PRV_GTCCRA..F from fsp/ra/fsp/src/r_gpt/r_gpt.c. The shadow buffer that feeds GTCCRA on the next reload is GTCCRC; the shadow buffer for GTCCRB is GTCCRE.

Enumerator
k_ra8_gpt_ccr_idx_a	RA8 GPT ccr index a.
k_ra8_gpt_ccr_idx_b	RA8 GPT ccr index b.
k_ra8_gpt_ccr_idx_c	RA8 GPT ccr index c.
k_ra8_gpt_ccr_idx_e	RA8 GPT ccr index e.

Definition at line 225 of file ra8_gpt.c.

◆ ra8_gpt_gtior_bits_t

enum ra8_gpt_gtior_bits_t : uint32_t

GTIOR field positions and masks.

From the RA8D2 device CMSIS header for R_GPT0_GTIOR (mirrored from HUM Ch 22.2.13 "GTIOR : General PWM Timer I/O Control Register", p 942..946):

GTIOA[4:0] bits 0..4
OADFLT bit 6
OAE bit 8
OADF[1:0] bits 9..10
GTIOB[4:0] bits 16..20
OBDFLT bit 22
OBE bit 24
OBDF[1:0] bits 25..26

The two GTIO sub-field encodings used by the polarity helper come from HUM Table 22.18 (GTIOA[4:0] / GTIOB[4:0] settings):

0x9 -> "low at compare match, high at cycle end" == active-high PWM
0x6 -> "high at compare match, low at cycle end" == active-low PWM

Enumerator
k_ra8_gpt_gtioa_mask	RA8 GPT gtioa mask.
k_ra8_gpt_gtioa_shift	RA8 GPT gtioa shift.
k_ra8_gpt_oadflt_mask	RA8 GPT oadflt mask.
k_ra8_gpt_oadflt_shift	RA8 GPT oadflt shift.
k_ra8_gpt_oae_mask	RA8 GPT oae mask.
k_ra8_gpt_oadf_mask	RA8 GPT oadf mask.
k_ra8_gpt_oadf_shift	RA8 GPT oadf shift.
k_ra8_gpt_gtiob_mask	RA8 GPT gtiob mask.
k_ra8_gpt_gtiob_shift	RA8 GPT gtiob shift.
k_ra8_gpt_obdflt_mask	RA8 GPT obdflt mask.
k_ra8_gpt_obdflt_shift	RA8 GPT obdflt shift.
k_ra8_gpt_obe_mask	RA8 GPT obe mask.
k_ra8_gpt_obdf_mask	RA8 GPT obdf mask.
k_ra8_gpt_obdf_shift	RA8 GPT obdf shift.
k_ra8_gpt_gtio_active_high	RA8 GPT gtio active high.
k_ra8_gpt_gtio_active_low	RA8 GPT gtio active low.

Definition at line 173 of file ra8_gpt.c.

◆ ra8_gptclkcr_bits_t

enum ra8_gptclkcr_bits_t : uint32_t

GTCLKCR block-level clock-control bits.

GTCLKCR is the GPT-bank-wide clock-domain register at 0x40323F10 (per k_ra8_gpt_gtclk_addr in ra8_gpt_regs.h). HUM Ch 22.2.47 "GTCLKCR : General PWM Timer Clock Control Register", p 974, plus HUM Ch 22.10.1 "Module-Stop Function Setting", p 1146, require GTCLKCR to be programmed BEFORE MSTPCRE.MSTPE31 (or any other GPT MSTP bit) is cleared. Without that step the per-channel bus side of the GPT block sits in an undefined clock-domain-crossing state and writes to GTWP / GTCR / etc. silently drop. Symptom on this chip: every J-Link or firmware read of 0x40322000 onward returns 0 even after MSTPCR is cleared.

BPEN = 1 ties GTCLK to PCLKA synchronously, which matches the project's CGC tree (no separate GPTCLK source via the CGC's GPTCKCR).

Enumerator
k_ra8_gptclkcr_bpen	BPEN: PCLKA <-> GTCLK sync.

Definition at line 83 of file ra8_gpt.c.

◆ ra8_gtwp_t

enum ra8_gtwp_t : uint32_t

GTWP write-protect key.

Enumerator
k_ra8_gtwp_key_unlock	Password in upper byte, WP=0.
k_ra8_gtwp_key_lock	Password in upper byte, WP=1.

Definition at line 58 of file ra8_gpt.c.

Function Documentation

◆ internal_dispatch()

void internal_dispatch	(	uint8_t	channel,
		uint32_t	status_mask )

static

Definition at line 883 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTST, k_ra8_gpt_channel_count, ra8_gpt(), RA8_INTERNAL, and s_gpt_state.

Referenced by ra8_gpt_dispatch_ccra(), ra8_gpt_dispatch_ccrb(), ra8_gpt_dispatch_ovf(), and ra8_gpt_dispatch_und().

◆ internal_gpt_clock_block_init()

void internal_gpt_clock_block_init ( void )

static

Block-level GPT clock-control init (one-shot, MSTP-stopped).

Programs GTCLKCR.BPEN=1 while every GPT channel's MSTP bit in MSTPCRE is still asserted (the chip-default reset state). The HUM Ch 22.10.1 p 1146 explicitly states "Set GTCLKCR register before releasing the module-stop state" and Ch 22.2.47 p 974 adds "Set first of initial setting after resetting. If MSTPCRE.MSTPE31 bit is 0, changing this register is prohibited". This helper must therefore run before the first ra8_mstp_enable(k_ra8_mstp_gptN) call. A static guard makes it idempotent: subsequent ra8_gpt_init calls on additional channels skip the write.

Precondition: At least one GPT channel's MSTP bit is still asserted (any channel works – the register is bank-wide, one instance).; The chip is running secure-mode or the firmware accesses 0x40323F10 via the secure alias.

Postcondition: GTCLKCR.BPEN == 1; the GPT bus interface is now in a defined clock-domain state and subsequent MSTP releases leave per-channel registers writable.; Subsequent calls become no-ops via the static guard.

Note: Not thread-safe; intended to run from single-threaded boot context before any GPT channel is enabled.

Since: 0.1.0

Definition at line 115 of file ra8_gpt.c.

References k_ra8_gpt_gtclk_addr, k_ra8_gptclkcr_bpen, and RA8_INTERNAL.

Referenced by ra8_gpt_init(), and ra8_gpt_start_free_run().

◆ internal_gtcr()

uint32_t internal_gtcr	(	ra8_gpt_mode_t	mode,
		ra8_gpt_prescaler_t	ps )

static

Definition at line 269 of file ra8_gpt.c.

References k_ra8_gpt_gtcr_md_shift, k_ra8_gpt_gtcr_tpcs_shift, and RA8_INTERNAL.

Referenced by ra8_gpt_init().

◆ internal_gtio_pattern()

uint32_t internal_gtio_pattern ( ra8_gpt_pwm_polarity_t polarity )

static

Build the GTIO[A/B] sub-field encoding for the requested polarity.

Parameters

[in] polarity Active-high or active-low.

Returns: 5-bit GTIO field value (0x9 active-high, 0x6 active-low).

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Return values

k_ra8_ok	Success path.
k_ra8_err_invalid_arg	Caller violated a precondition.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Since: 0.1.0

Definition at line 669 of file ra8_gpt.c.

References k_ra8_gpt_gtio_active_high, k_ra8_gpt_gtio_active_low, k_ra8_gpt_pol_active_low, and RA8_INTERNAL.

Referenced by ra8_gpt_pwm_pin_configure().

◆ internal_three_phase_init_subs()

ra8_err_t internal_three_phase_init_subs	(	const ra8_gpt_three_phase_cfg_t *	cfg,
		uint32_t *	out_mask )

static

Bring up the three GPT submodules and build the start mask.

Parameters

[in]	cfg	Three-phase configuration descriptor.
[out]	out_mask	Combined channel-bit mask on success.

Returns: k_ra8_ok or the first failing channel's error code.

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Since: 0.1.0

Return values

k_ra8_ok	Success path.
k_ra8_err_invalid_arg	Caller violated a precondition.

Definition at line 767 of file ra8_gpt.c.

References ra8_gpt_three_phase_cfg_t::channels, ra8_gpt_three_phase_cfg_t::initial_duty_u, ra8_gpt_three_phase_cfg_t::initial_duty_v, ra8_gpt_three_phase_cfg_t::initial_duty_w, k_ra8_gpt_three_phase_count, k_ra8_ok, ra8_gpt_three_phase_cfg_t::mode, ra8_gpt_three_phase_cfg_t::period_counts, ra8_gpt_three_phase_cfg_t::prescaler, ra8_gpt_deinit(), ra8_gpt_init(), RA8_INTERNAL, and s_three_phase.

Referenced by ra8_gpt_three_phase_open().

◆ ra8_gpt_attach_handler()

ra8_err_t ra8_gpt_attach_handler	(	uint8_t	channel,
		ra8_gpt_event_fn_t	fn,
		void *	ctx )

nodiscard

Attach a GPT event callback for a channel.

Parameters

[in]	channel	GPT channel.
[in]	fn	Callback fired on ISR dispatch.
[in]	ctx	Context passed to the callback.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 429 of file ra8_gpt.c.

References k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, k_ra8_ok, and s_gpt_state.

◆ ra8_gpt_capture_configure()

ra8_err_t ra8_gpt_capture_configure	(	uint8_t	channel,
		ra8_gpt_ccr_sel_t	which,
		uint32_t	source_mask )

nodiscard

Arm a GPT channel for input capture on GTCCRA or GTCCRB.

Writes source_mask into GTICASR (when which is k_ra8_gpt_ccr_a) or GTICBSR (when which is k_ra8_gpt_ccr_b) inside a GTWP write-protect window. A non-zero mask switches the selected GTCCR register from output-compare to input-capture: each selected edge latches GTCNT into the register and raises the matching GTST flag (read via ra8_gpt_get_status). Passing k_ra8_gpt_cap_src_none returns the register to output-compare use.

The counter itself is unaffected – start it on the internal clock with ra8_gpt_init (or ra8_gpt_start_free_run) so GTCNT advances between captures; the difference between two captures is the measured period in counter ticks.

Parameters

[in]	channel	GPT channel 0..13.
[in]	which	Target capture register: A (GTCCRA) or B (GTCCRB).
[in]	source_mask	OR of k_ra8_gpt_cap_src_* bits; must lie within k_ra8_gpt_cap_src_valid_mask.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Capture source programmed.
k_ra8_err_null_ptr	channel out of range.
k_ra8_err_invalid_arg	which out of range or source_mask sets a reserved bit.

Precondition: Channel previously initialized via ra8_gpt_init / ra8_gpt_start_free_run.; IRQs masked or single-threaded init context.

Postcondition: GTICASR (A) or GTICBSR (B) equals source_mask.; GTWP is re-locked.

Note: Thread safety: not thread-safe.

See also: ra8_gpt_capture_read() Read the latched GTCNT value.; ra8_gpt_get_status() Poll the TCFA / TCFB capture flag.

Since: 0.1.0

HUM:: Ch 22.2.10 "GTICASR : General PWM Timer Input Capture Source Select Register A" p 906-908. Ch 22.2.11 "GTICBSR : General PWM Timer Input Capture Source Select Register B" p 909-912. Ch 22.2.1 "GTWP : General PWM Timer Write Protection Register" p 883-884.

Definition at line 528 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTICASR, r_gpt_channel_regs_t::GTICBSR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_gpt_cap_src_valid_mask, k_ra8_gpt_ccr_a, k_ra8_gpt_ccr_b, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by gpt_ecc_timers_or_halt().

◆ ra8_gpt_capture_read()

ra8_err_t ra8_gpt_capture_read	(	uint8_t	channel,
		ra8_gpt_ccr_sel_t	which,
		uint32_t *	out_value )

nodiscard

Read the value latched by the last input capture.

Reads GTCCRA (which == k_ra8_gpt_ccr_a) or GTCCRB (which == k_ra8_gpt_ccr_b), which hold the GTCNT value latched on the most recent capture edge while the matching source register is armed. The caller typically polls ra8_gpt_get_status for TCFA / TCFB, reads the value here, then clears the flag with ra8_gpt_clear_status.

Parameters

[in]	channel	GPT channel 0..13.
[in]	which	Source capture register: A (GTCCRA) or B (GTCCRB).
[out]	out_value	Receives the latched 32-bit counter value.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Value read into out_value.
k_ra8_err_null_ptr	out_value NULL or channel out of range.
k_ra8_err_invalid_arg	which out of range.

Precondition: ra8_gpt_capture_configure armed the register being read.; out_value points to writable storage.

Postcondition: *out_value holds the latched GTCCR value on success.; No register is modified (read-only path).

Note: Thread safety: not thread-safe.

See also: ra8_gpt_capture_configure()

Since: 0.1.0

HUM:: Ch 22.2.20 "GTCCRk : General PWM Timer Compare Capture Register k (k = A to F)" p 938.

Definition at line 553 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCCR, k_ra8_err_invalid_arg, k_ra8_gpt_ccr_b, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by gpt_ecc_service_capture().

◆ ra8_gpt_clear_status()

ra8_err_t ra8_gpt_clear_status	(	uint8_t	channel,
		uint32_t	mask )

nodiscard

Clear GTST flag bits (write-0 to clear).

Since: 0.1.0

Definition at line 418 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTST, k_ra8_gpt_gtst_mask, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by gpt_ecc_service_capture(), and internal_wait_ovf().

◆ ra8_gpt_counter_set()

ra8_err_t ra8_gpt_counter_set	(	uint8_t	channel,
		uint32_t	value )

nodiscard

Force GTCNT to value (timer must be stopped).

Mirrors FSP R_GPT_CounterSet – the underlying register is not safe to write while the counter is running, so the call rejects any channel whose GTCR.CST bit is set.

Parameters

[in]	channel	GPT channel 0..13.
[in]	value	New GTCNT value.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Counter updated.
k_ra8_err_null_ptr	channel out of range.
k_ra8_err_invalid_state	Counter is currently running.

Precondition: Timer counter is stopped (GTCR.CST == 0).; IRQs masked or single-threaded init context.

Postcondition: GTCNT holds value.; GTCR.CST is unchanged.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.19 "GTCNT : General PWM Timer Counter", p 980..981.

Definition at line 637 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCNT, r_gpt_channel_regs_t::GTCR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_state, k_ra8_gpt_gtcr_cst_mask, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_dead_time_set()

ra8_err_t ra8_gpt_dead_time_set	(	uint8_t	channel,
		uint32_t	rising_dt,
		uint32_t	falling_dt )

nodiscard

Programme the dead-time value pair for complementary PWM.

Writes GTDVU (rising-edge dead-time) and GTDVD (falling-edge dead-time) and asserts GTDTCR.TDE (dead-time enable) iff at least one of the two values is non-zero. Mirrors the dead-time branch of FSP gpt_hardware_initialize.

Parameters

[in]	channel	GPT channel 0..13.
[in]	rising_dt	Dead-time count for the rising edge (GTDVU).
[in]	falling_dt	Dead-time count for the falling edge (GTDVD).

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Dead-time programmed.
k_ra8_err_null_ptr	channel out of range.

Precondition: Channel previously initialized via ra8_gpt_init.; IRQs masked or single-threaded init context.

Postcondition: GTDVU == rising_dt and GTDVD == falling_dt.; GTDTCR.TDE bit is set iff either input is non-zero.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.27 "GTDTCR : General PWM Timer Dead Time Control Register", p 998..999. Ch 22.2.28 "GTDVU/GTDVD", p 1000..1001.

Definition at line 716 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTDTCR, r_gpt_channel_regs_t::GTDVD, r_gpt_channel_regs_t::GTDVU, r_gpt_channel_regs_t::GTWP, k_ra8_gpt_gtdtcr_tde, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by internal_motor_3phase_pin_configure_all().

◆ ra8_gpt_deinit()

ra8_err_t ra8_gpt_deinit ( uint8_t channel )

nodiscard

Tear down a channel (stop + MSTP release).

Since: 0.1.0

Definition at line 365 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCR, r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTWP, k_ra8_gpt_gtstp_stop, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), ra8_mstp_disable(), s_gpt_mstp_table, s_gpt_state, and s_tag.

Referenced by internal_three_phase_init_subs(), and ra8_gpt_three_phase_close().

◆ ra8_gpt_dispatch_ccra()

void ra8_gpt_dispatch_ccra ( uint8_t channel )

Dispatch GPT compare-match A (GTCIA) – clear + fire callback.

Parameters

[in] channel GPT channel.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 913 of file ra8_gpt.c.

References internal_dispatch(), and k_ra8_gpt_status_ccra.

◆ ra8_gpt_dispatch_ccrb()

void ra8_gpt_dispatch_ccrb ( uint8_t channel )

Dispatch GPT compare-match B (GTCIB) – clear + fire callback.

Parameters

[in] channel GPT channel.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 919 of file ra8_gpt.c.

References internal_dispatch(), and k_ra8_gpt_status_ccrb.

◆ ra8_gpt_dispatch_ovf()

void ra8_gpt_dispatch_ovf ( uint8_t channel )

Dispatch GPT overflow (GTCIV) – clear + fire callback.

Parameters

[in] channel GPT channel.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 901 of file ra8_gpt.c.

References internal_dispatch(), and k_ra8_gpt_status_overflow.

◆ ra8_gpt_dispatch_und()

void ra8_gpt_dispatch_und ( uint8_t channel )

Dispatch GPT underflow (GTCIU) – clear + fire callback.

Parameters

[in] channel GPT channel.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 907 of file ra8_gpt.c.

References internal_dispatch(), and k_ra8_gpt_status_underflow.

◆ ra8_gpt_duty_cycle_set()

ra8_err_t ra8_gpt_duty_cycle_set	(	uint8_t	channel,
		ra8_gpt_pwm_pin_t	pin,
		uint32_t	compare_counts )

nodiscard

Update one PWM compare value via the shadow buffer.

Writes compare_counts into GTCCRC (for k_ra8_gpt_pin_a) or GTCCRE (for k_ra8_gpt_pin_b). Per FSP R_GPT_DutyCycleSet the buffer registers are swapped into GTCCRA/GTCCRB at the next cycle end, so PWM transitions are glitch-free. The GTBER.CCRA / GTBER.CCRB single-buffer enable bits are also asserted so the swap actually happens.

Parameters

[in]	channel	GPT channel 0..13.
[in]	pin	Which output pin – A or B.
[in]	compare_counts	New compare value (must be <= period).

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Compare buffer programmed.
k_ra8_err_invalid_arg	pin not in ra8_gpt_pwm_pin_t.
k_ra8_err_null_ptr	channel out of range.

Precondition: Channel previously initialized via ra8_gpt_init.; Caller has ensured compare_counts <= GTPR.

Postcondition: GTCCRC / GTCCRE holds the new value.; GTBER buffer-enable bit for the selected pin is asserted.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.20 "GTCCRA..F : General PWM Timer Compare/Capture Registers", p 982..984. Ch 22.2.17 "GTBER : General PWM Timer Buffer Enable Register", p 965..968.

Definition at line 613 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTBER, r_gpt_channel_regs_t::GTCCR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_gpt_ccr_idx_c, k_ra8_gpt_ccr_idx_e, k_ra8_gpt_gtber_ccra_single, k_ra8_gpt_gtber_ccrb_single, k_ra8_gpt_pin_a, k_ra8_gpt_pin_b, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, pin, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_enter_stop()

ra8_err_t ra8_gpt_enter_stop ( uint8_t channel )

nodiscard

Put a channel into MSTP-gated stop.

Since: 0.1.0

Definition at line 439 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, k_ra8_gpt_gtstp_stop, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, ra8_gpt(), ra8_mstp_disable(), and s_gpt_mstp_table.

◆ ra8_gpt_event_count_configure()

ra8_err_t ra8_gpt_event_count_configure	(	uint8_t	channel,
		uint32_t	up_source,
		uint32_t	down_source )

nodiscard

Configure external event (edge) counting on GTCNT.

Writes up_source into GTUPSR and down_source into GTDNSR inside a GTWP write-protect window. When either register is non-zero the channel leaves internal-clock counting and instead increments GTCNT on each selected up edge and decrements it on each selected down edge – the primitive for external-pulse counting (up source only) and quadrature-encoder decoding (paired up / down sources). Passing k_ra8_gpt_cnt_src_none for both arguments returns the channel to internal-clock counting.

Start the counter separately (ra8_gpt_init with auto_start or ra8_gpt_start_free_run); GTCR.CST still gates whether edges are counted. GTCR.TPCS and the GTCR.MD waveform mode have no effect while an event-count source is active.

Parameters

[in]	channel	GPT channel 0..13.
[in]	up_source	OR of k_ra8_gpt_cnt_src_* up-count bits; must lie within k_ra8_gpt_cnt_src_valid_mask.
[in]	down_source	OR of k_ra8_gpt_cnt_src_* down-count bits; must lie within k_ra8_gpt_cnt_src_valid_mask.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Up / down sources programmed.
k_ra8_err_null_ptr	channel out of range.
k_ra8_err_invalid_arg	up_source or down_source sets a reserved bit.

Precondition: Channel previously initialized via ra8_gpt_init.; IRQs masked or single-threaded init context.

Postcondition: GTUPSR == up_source and GTDNSR == down_source.; GTWP is re-locked.

Note: Thread safety: not thread-safe.

See also: ra8_gpt_read() Read the accumulated GTCNT edge count.

Since: 0.1.0

HUM:: Ch 22.2.8 "GTUPSR : General PWM Timer Up Count Source Select Register" p 898-901. Ch 22.2.9 "GTDNSR : General PWM Timer Down Count Source Select Register" p 902-905. Ch 22.2.1 "GTWP : General PWM Timer Write Protection Register" p 883-884.

Definition at line 569 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTDNSR, r_gpt_channel_regs_t::GTUPSR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_gpt_cnt_src_valid_mask, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by gpt_ecc_timers_or_halt().

◆ ra8_gpt_exit_stop()

ra8_err_t ra8_gpt_exit_stop ( uint8_t channel )

nodiscard

Exit MSTP-gated stop.

Since: 0.1.0

Definition at line 453 of file ra8_gpt.c.

References k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, ra8_mstp_enable(), and s_gpt_mstp_table.

◆ ra8_gpt_get_status()

ra8_err_t ra8_gpt_get_status	(	uint8_t	channel,
		uint32_t *	out_mask )

nodiscard

Read GTST overflow / underflow / compare flags.

Parameters

[in]	channel	GPT channel.
[out]	out_mask	OR of k_ra8_gpt_status_*.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 408 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTST, k_ra8_gpt_gtst_mask, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by gpt_ecc_service_capture(), and internal_wait_ovf().

◆ ra8_gpt_init()

ra8_err_t ra8_gpt_init	(	uint8_t	channel,
		const ra8_gpt_cfg_t *	cfg )

nodiscard

Initialise a GPT channel with a full config descriptor.

Parameters

[in]	channel	GPT channel (0..13).
[in]	cfg	Non-NULL configuration descriptor.

Returns: ra8_err_t error code.

Precondition: IRQs masked or single-threaded init context.; ra8_mstp_init has been called.

Postcondition: On success, GTCR + GTPR + GTCCR are programmed and (if cfg->auto_start) GTSTR is set.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 329 of file ra8_gpt.c.

Referenced by gpt_ecc_timers_or_halt(), internal_arm(), internal_arm_channel(), internal_gpt_irq_demo_arm(), internal_gpt_pwm_demo_arm(), internal_poeg_demo_arm_gpt(), internal_setup_or_halt(), internal_three_phase_init_subs(), ra8_board_camera_xclk_start(), and ra8_nsc_gpt_init().

◆ ra8_gpt_period_set()

ra8_err_t ra8_gpt_period_set	(	uint8_t	channel,
		uint32_t	period_counts )

nodiscard

Update the GPT period via the shadow buffer (GTPBR).

Writes period_counts to GTPBR; on the next overflow the timer loads GTPBR into GTPR. If the counter is currently stopped the value is also written into GTPR immediately and the counter is cleared so the next ra8_gpt_set_period style call has the same starting point as a fresh ra8_gpt_init. Mirrors FSP R_GPT_PeriodSet from fsp/ra/fsp/src/r_gpt/r_gpt.c.

Parameters

[in]	channel	GPT channel 0..13.
[in]	period_counts	New period in counter ticks.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Period buffer programmed.
k_ra8_err_null_ptr	channel out of range.

Precondition: Channel previously initialized via ra8_gpt_init.; IRQs masked or single-threaded init context.

Postcondition: GTPBR holds period_counts.; On the next overflow GTPR is reloaded from GTPBR.

Note: Thread safety: not thread-safe.

See also: ra8_gpt_set_period() Legacy single-shot variant (no buffer).

Since: 0.1.0

HUM:: Ch 22.2.21 "GTPR : General PWM Timer Cycle Setting Register", p 985..986.

Definition at line 595 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCNT, r_gpt_channel_regs_t::GTCR, r_gpt_channel_regs_t::GTPBR, r_gpt_channel_regs_t::GTPR, r_gpt_channel_regs_t::GTWP, k_ra8_gpt_gtcr_cst_mask, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_pwm_pin_configure()

ra8_err_t ra8_gpt_pwm_pin_configure	(	uint8_t	channel,
		ra8_gpt_pwm_pin_t	pin,
		const ra8_gpt_pwm_pin_cfg_t *	cfg )

nodiscard

Configure GTIOR for one PWM output pin.

Programmes the polarity, output-enable, stop level, and output-disable-on-POEG-fault behaviour for either GTIOCnA or GTIOCnB. Mirrors the GTIOR-write portion of FSP R_GPT_OutputEnable / R_GPT_OutputDisable and the PWM setup logic in gpt_hardware_initialize.

Parameters

[in]	channel	GPT channel 0..13.
[in]	pin	Which output pin – A or B.
[in]	cfg	Non-NULL configuration descriptor.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Pin configured.
k_ra8_err_null_ptr	channel out of range or cfg NULL.
k_ra8_err_invalid_arg	pin not in ra8_gpt_pwm_pin_t.

Precondition: Channel previously initialized via ra8_gpt_init.; IRQs masked or single-threaded init context.

Postcondition: GTIOR fields for the selected pin reflect cfg.; GTIOR fields for the other pin are preserved.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.13 "GTIOR : General PWM Timer I/O Control Register", p 942..946 – bit 8 OAE, bit 24 OBE, bit 6 OADFLT, bit 22 OBDFLT, bits [9..10] OADF, bits [25..26] OBDF, bits [0..4] GTIOA[4:0], bits [16..20] GTIOB[4:0].

Definition at line 678 of file ra8_gpt.c.

References ra8_gpt_pwm_pin_cfg_t::disable_on_fault, r_gpt_channel_regs_t::GTIOR, r_gpt_channel_regs_t::GTWP, internal_gtio_pattern(), k_ra8_err_invalid_arg, k_ra8_gpt_gtioa_mask, k_ra8_gpt_gtioa_shift, k_ra8_gpt_gtiob_mask, k_ra8_gpt_gtiob_shift, k_ra8_gpt_oadf_mask, k_ra8_gpt_oadf_shift, k_ra8_gpt_oadflt_mask, k_ra8_gpt_oadflt_shift, k_ra8_gpt_oae_mask, k_ra8_gpt_obdf_mask, k_ra8_gpt_obdf_shift, k_ra8_gpt_obdflt_mask, k_ra8_gpt_obdflt_shift, k_ra8_gpt_obe_mask, k_ra8_gpt_pin_a, k_ra8_gpt_pin_b, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, ra8_gpt_pwm_pin_cfg_t::output_enable, pin, ra8_gpt_pwm_pin_cfg_t::polarity, RA8_CHECK_NULL_PTR, ra8_gpt(), s_tag, and ra8_gpt_pwm_pin_cfg_t::stop_level.

Referenced by internal_motor_3phase_pin_configure_all(), and ra8_board_camera_xclk_start().

◆ ra8_gpt_read()

ra8_err_t ra8_gpt_read	(	uint8_t	channel,
		uint32_t *	out )

nodiscard

Read the current counter value.

Parameters

[in]	channel	GPT channel (0..13).
[out]	out	Receive counter value.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 314 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCNT, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by cam_run(), internal_poeg_demo_cycle(), internal_read(), main(), ra8_nsc_gpt_read(), and timer_demo_one_capture().

◆ ra8_gpt_read_dma()

ra8_err_t ra8_gpt_read_dma	(	uint8_t	channel,
		uint32_t *	out_counts,
		uint16_t	count,
		ra8_dma_complete_fn_t	on_complete,
		void *	ctx,
		uint8_t *	out_dma_channel )

nodiscard

Capture a stream of GTCNT values into a buffer via DMA.

Programmes the ra8_dma substrate to copy count 32-bit counter snapshots from the channel's GTCNT register into out_counts[]. This is the "capture streaming" DMA RX path from the roadmap note – the driver samples GTCNT on each ELC trigger and stores the value, so the host sees the full capture sequence without ISR overhead.

Parameters

[in]	channel	GPT channel 0..13.
[out]	out_counts	Destination counter buffer. Must outlive the transfer.
[in]	count	Number of samples; non-zero.
[in]	on_complete	Completion callback. May be NULL.
[in]	ctx	Context passed to on_complete.
[out]	out_dma_channel	Allocated DMAC channel on success.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Transfer armed.
k_ra8_err_null_ptr	out_counts / out_dma_channel NULL.
k_ra8_err_invalid_arg	Channel or count invalid.
k_ra8_err_no_mem	All DMAC channels in use.
k_ra8_err_hw_error	ra8_dma_request failed.

Precondition: Channel previously initialized via ra8_gpt_init.; ra8_dma_init has been called.

Postcondition: On success, DMAC channel is armed.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 493 of file ra8_gpt.c.

References ra8_dma_request_t::count, ra8_dma_request_t::ctx, ra8_dma_request_t::dst_addr, ra8_dma_request_t::dst_inc, r_gpt_channel_regs_t::GTCNT, k_ra8_dmac_width_word, k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, ra8_dma_request_t::on_complete, RA8_CHECK_NULL_PTR, ra8_dma_request(), ra8_gpt(), s_tag, ra8_dma_request_t::src_addr, ra8_dma_request_t::src_inc, ra8_dma_request_t::trigger, and ra8_dma_request_t::width.

◆ ra8_gpt_set_duty()

ra8_err_t ra8_gpt_set_duty	(	uint8_t	channel,
		ra8_gpt_ccr_sel_t	which,
		uint32_t	value )

nodiscard

Change one compare register (GTCCRA / GTCCRB) at runtime.

Parameters

[in]	channel	GPT channel.
[in]	which	Which compare register.
[in]	value	New compare value.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 394 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCCR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_gpt_ccr_b, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

Referenced by main().

◆ ra8_gpt_set_period()

ra8_err_t ra8_gpt_set_period	(	uint8_t	channel,
		uint32_t	period )

nodiscard

Change the GPT period (GTPR / GTPBR) at runtime.

Parameters

[in]	channel	GPT channel.
[in]	period	New GTPR value.

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 382 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTPBR, r_gpt_channel_regs_t::GTPR, r_gpt_channel_regs_t::GTWP, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_start_free_run()

ra8_err_t ra8_gpt_start_free_run	(	uint8_t	channel,
		uint32_t	period )

nodiscard

Configure a GPT channel as a free-running up-counter.

Parameters

[in]	channel	GPT channel (0..13).
[in]	period	Period in timer ticks (write to GTPR).

Returns: ra8_err_t error code.

Note: The counter runs from PCLKD (or a configurable source) with no prescaler. The caller is responsible for choosing a sensible period value given the current PCLKD.

Since: 0.1.0

Definition at line 274 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTCNT, r_gpt_channel_regs_t::GTCR, r_gpt_channel_regs_t::GTPR, r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTSTR, r_gpt_channel_regs_t::GTWP, internal_gpt_clock_block_init(), k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), ra8_log_info_val, ra8_mstp_enable(), RA8_RETURN_ON_ERROR, s_gpt_mstp_table, and s_tag.

Referenced by internal_gpt_irq_demo_arm(), main(), and timer_demo_setup_or_halt().

◆ ra8_gpt_stop()

ra8_err_t ra8_gpt_stop ( uint8_t channel )

nodiscard

Stop a GPT channel.

Parameters

[in] channel GPT channel (0..13).

Returns: ra8_err_t error code.

Since: 0.1.0

Definition at line 303 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTWP, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), and s_tag.

◆ ra8_gpt_three_phase_close()

ra8_err_t ra8_gpt_three_phase_close ( void )

nodiscard

Stop and tear down the three U/V/W channels.

Stops the three channels via a single GTSTP write and calls ra8_gpt_deinit on each. Mirrors FSP R_GPT_THREE_PHASE_Stop + R_GPT_THREE_PHASE_Close.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	All three channels closed.
k_ra8_err_invalid_state	ra8_gpt_three_phase_open not called.

Precondition: ra8_gpt_three_phase_open returned k_ra8_ok.; IRQs masked or single-threaded shutdown context.

Postcondition: All three channels are stopped and MSTP-released.; Three-phase state is marked closed.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 860 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTSTP, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_state, k_ra8_gpt_three_phase_count, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, ra8_gpt(), ra8_gpt_deinit(), and s_three_phase.

◆ ra8_gpt_three_phase_open()

ra8_err_t ra8_gpt_three_phase_open ( const ra8_gpt_three_phase_cfg_t * cfg )

nodiscard

Open three GPT channels as a phase-synchronized U/V/W triple.

Calls ra8_gpt_init on each of the three channels in cfg->channels with the same mode, prescaler, and period. After all three are configured, the U-channel's GTSTR is written with a bitmask covering all three channel positions so they start on the same PCLKD edge. Mirrors FSP R_GPT_THREE_PHASE_Open + R_GPT_THREE_PHASE_Start.

Parameters

[in] cfg Non-NULL three-phase configuration descriptor.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	All three channels opened and started.
k_ra8_err_null_ptr	cfg NULL.
k_ra8_err_invalid_arg	Any channel id out of range or already open.

Precondition: ra8_mstp_init has been called.; IRQs masked or single-threaded init context.

Postcondition: All three GPT channels are configured and counting.; Driver-internal three-phase state is marked open.

Note: Thread safety: not thread-safe.

Since: 0.1.0

HUM:: Ch 22.2.2 "GTSTR : General PWM Timer Software Start Register", p 901 – writing multiple CSTRTn bits in one access starts those channels synchronously.

Definition at line 799 of file ra8_gpt.c.

References ra8_gpt_three_phase_cfg_t::channels, r_gpt_channel_regs_t::GTSTR, r_gpt_channel_regs_t::GTWP, internal_three_phase_init_subs(), k_ra8_err_invalid_arg, k_ra8_err_invalid_state, k_ra8_gpt_channel_count, k_ra8_gpt_three_phase_count, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_gpt(), ra8_log_info_val, s_tag, and s_three_phase.

Referenced by internal_gpt_3p_demo_arm(), and internal_motor_3phase_init_pwm().

◆ ra8_gpt_three_phase_set_duty()

ra8_err_t ra8_gpt_three_phase_set_duty	(	uint32_t	u_duty,
		uint32_t	v_duty,
		uint32_t	w_duty )

nodiscard

Atomically update U/V/W compare values via the shadow buffer.

Writes u_duty / v_duty / w_duty into the GTCCRC and GTCCRE shadow buffers of the three channels recorded by ra8_gpt_three_phase_open. The GTBER buffer-enable bit makes the swap into GTCCRA/B happen at the next cycle end, so all three phases update on the same overflow. Mirrors FSP R_GPT_THREE_PHASE_DutyCycleSet.

Parameters

[in]	u_duty	New U-phase compare value.
[in]	v_duty	New V-phase compare value.
[in]	w_duty	New W-phase compare value.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Compare values queued for swap.
k_ra8_err_invalid_state	ra8_gpt_three_phase_open not called.
k_ra8_err_invalid_arg	Any duty value > GTPR.

Precondition: ra8_gpt_three_phase_open returned k_ra8_ok.; All three duty values <= the shared period.

Postcondition: GTCCRC and GTCCRE on each channel hold the new duty.; Three-phase state is still open.

Note: Thread safety: not thread-safe. Recommended to call from a high-priority ISR per FSP r_gpt_three_phase guidance.

Since: 0.1.0

HUM:: Ch 22.2.20 "GTCCRA..F", p 982..984. Ch 22.2.17 "GTBER", p 965.

Definition at line 833 of file ra8_gpt.c.

References r_gpt_channel_regs_t::GTBER, r_gpt_channel_regs_t::GTCCR, r_gpt_channel_regs_t::GTPR, r_gpt_channel_regs_t::GTWP, k_ra8_err_invalid_arg, k_ra8_err_invalid_state, k_ra8_gpt_ccr_idx_c, k_ra8_gpt_ccr_idx_e, k_ra8_gpt_gtber_ccra_single, k_ra8_gpt_gtber_ccrb_single, k_ra8_gpt_three_phase_count, k_ra8_gtwp_key_lock, k_ra8_gtwp_key_unlock, k_ra8_ok, ra8_gpt(), and s_three_phase.

Referenced by internal_motor_3phase_init_pwm(), and main().

◆ ra8_gpt_write_dma()

ra8_err_t ra8_gpt_write_dma	(	uint8_t	channel,
		const uint32_t *	periods,
		uint16_t	count,
		ra8_dma_complete_fn_t	on_complete,
		void *	ctx,
		uint8_t *	out_dma_channel )

nodiscard

Stream a buffer of period values into GPT GTPR via DMA.

Programmes the ra8_dma substrate to copy count 32-bit period values from periods[] into the channel's GTPR register. This is the "sample streaming" DMA TX path from the roadmap note – the driver pumps a preloaded period sequence into the timer without the CPU touching GTPR each tick.

Parameters

[in]	channel	GPT channel 0..13.
[in]	periods	Source array of 32-bit period values. Must outlive the transfer.
[in]	count	Number of periods; non-zero.
[in]	on_complete	Completion callback. May be NULL.
[in]	ctx	Context passed to on_complete.
[out]	out_dma_channel	Allocated DMAC channel on success.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Transfer armed.
k_ra8_err_null_ptr	periods / out_dma_channel NULL.
k_ra8_err_invalid_arg	Channel or count invalid.
k_ra8_err_no_mem	All DMAC channels in use.
k_ra8_err_hw_error	ra8_dma_request failed.

Precondition: Channel previously initialized via ra8_gpt_init.; ra8_dma_init has been called.

Postcondition: On success, DMAC channel is armed.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 463 of file ra8_gpt.c.

References ra8_dma_request_t::count, ra8_dma_request_t::ctx, ra8_dma_request_t::dst_addr, ra8_dma_request_t::dst_inc, r_gpt_channel_regs_t::GTPR, k_ra8_dmac_width_word, k_ra8_err_invalid_arg, k_ra8_gpt_channel_count, ra8_dma_request_t::on_complete, RA8_CHECK_NULL_PTR, ra8_dma_request(), ra8_gpt(), s_tag, ra8_dma_request_t::src_addr, ra8_dma_request_t::src_inc, ra8_dma_request_t::trigger, and ra8_dma_request_t::width.

Referenced by internal_run_one().

Variable Documentation

◆ s_gpt_mstp_table

const ra8_mstp_t s_gpt_mstp_table[k_ra8_gpt_channel_count]

static

Initial value:

                                         = {
  k_ra8_mstp_gpt0,
  k_ra8_mstp_gpt1,
  k_ra8_mstp_gpt2,
  k_ra8_mstp_gpt3,
  k_ra8_mstp_gpt4_9,
  k_ra8_mstp_gpt4_9,
  k_ra8_mstp_gpt4_9,
  k_ra8_mstp_gpt4_9,
  k_ra8_mstp_gpt4_9,
  k_ra8_mstp_gpt4_9,
  k_ra8_mstp_gpt10,
  k_ra8_mstp_gpt11,
  k_ra8_mstp_gpt12,
  k_ra8_mstp_gpt13,
}

Channel-index -> MSTP id lookup.

GPT4..GPT9 share a single bit (MSTPE27); the other channels each have their own. Sized by k_ra8_gpt_channel_count from ra8_gpt_regs.h. HUM Ch 11.2.10 "MSTPCRE", p 449..450.

Definition at line 37 of file ra8_gpt.c.

Referenced by ra8_gpt_deinit(), ra8_gpt_enter_stop(), ra8_gpt_exit_stop(), ra8_gpt_init(), and ra8_gpt_start_free_run().

◆ s_gpt_state

ra8_gpt_state_t s_gpt_state[k_ra8_gpt_channel_count]

static

Definition at line 266 of file ra8_gpt.c.

Referenced by internal_dispatch(), ra8_gpt_attach_handler(), ra8_gpt_deinit(), and ra8_gpt_init().

◆ s_tag

const char* s_tag = "GPT"

static

Definition at line 28 of file ra8_gpt.c.

◆ s_three_phase

ra8_gpt_three_phase_state_t s_three_phase

static

Definition at line 746 of file ra8_gpt.c.

Referenced by internal_three_phase_init_subs(), ra8_gpt_three_phase_close(), ra8_gpt_three_phase_open(), and ra8_gpt_three_phase_set_duty().

Data Structures

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ ra8_gpt_bits_t

◆ ra8_gpt_buffer_bits_t

◆ ra8_gpt_ccr_idx_t

◆ ra8_gpt_gtior_bits_t

◆ ra8_gptclkcr_bits_t

◆ ra8_gtwp_t

Function Documentation

◆ internal_dispatch()

◆ internal_gpt_clock_block_init()

◆ internal_gtcr()

◆ internal_gtio_pattern()

◆ internal_three_phase_init_subs()

◆ ra8_gpt_attach_handler()

◆ ra8_gpt_capture_configure()

◆ ra8_gpt_capture_read()

◆ ra8_gpt_clear_status()

◆ ra8_gpt_counter_set()

◆ ra8_gpt_dead_time_set()

◆ ra8_gpt_deinit()

◆ ra8_gpt_dispatch_ccra()

◆ ra8_gpt_dispatch_ccrb()

◆ ra8_gpt_dispatch_ovf()

◆ ra8_gpt_dispatch_und()

◆ ra8_gpt_duty_cycle_set()

◆ ra8_gpt_enter_stop()

◆ ra8_gpt_event_count_configure()

◆ ra8_gpt_exit_stop()

◆ ra8_gpt_get_status()

◆ ra8_gpt_init()

◆ ra8_gpt_period_set()

◆ ra8_gpt_pwm_pin_configure()

◆ ra8_gpt_read()

◆ ra8_gpt_read_dma()

◆ ra8_gpt_set_duty()

◆ ra8_gpt_set_period()

◆ ra8_gpt_start_free_run()

◆ ra8_gpt_stop()

◆ ra8_gpt_three_phase_close()

◆ ra8_gpt_three_phase_open()

◆ ra8_gpt_three_phase_set_duty()

◆ ra8_gpt_write_dma()

Variable Documentation

◆ s_gpt_mstp_table

◆ s_gpt_state

◆ s_tag

◆ s_three_phase