General PWM Timer (GPT) register layout for the Renesas RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_gpt_regs.h:

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Data Structures
struct	r_gpt_channel_regs_t
	Per-channel GPT register window. More...

Enumerations
enum	ra8_gpt_addr_t : uintptr_t { k_ra8_gpt0_base_addr = 0x40322000UL , k_ra8_gpt_gtclk_addr = 0x40323F10UL , k_ra8_gpt_odc_base_addr = 0x40324000UL , k_ra8_gpt_ops_base_addr = 0x40323F00UL }
enum	ra8_gpt_limits_t : uint16_t { k_ra8_gpt_channel_count = 14U , k_ra8_gpt_channel_stride = 0x100U }

Functions
static volatile r_gpt_channel_regs_t *	ra8_gpt (uint8_t channel)
	Get pointer to GPT channel N.

Detailed Description

General PWM Timer (GPT) register layout for the Renesas RA8D2.

RA8D2 exposes 14 GPT channels (GPT0..GPT13) at 0x40322000 with a 0x100 stride per channel. Each channel is a 32-bit up/down counter with independent GTIOA/GTIOB outputs, PWM / compare-match modes, dead-time control, and ADC trigger hooks. A small set of shared registers (GTCLK, GTODC, GTOPS) lives at higher offsets.

The per-channel struct below models the most frequently touched registers; extend as drivers need.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_gpt_regs.h.

Enumeration Type Documentation

◆ ra8_gpt_addr_t

enum ra8_gpt_addr_t : uintptr_t

Enumerator
k_ra8_gpt0_base_addr	RA8 gpt0 base address.
k_ra8_gpt_gtclk_addr	Shared GTCLK regs.
k_ra8_gpt_odc_base_addr	Output Disable Control.
k_ra8_gpt_ops_base_addr	Output Phase Switching.

Definition at line 30 of file ra8_gpt_regs.h.

◆ ra8_gpt_limits_t

enum ra8_gpt_limits_t : uint16_t

Enumerator
k_ra8_gpt_channel_count	RA8 GPT channel count.
k_ra8_gpt_channel_stride	RA8 GPT channel stride.

Definition at line 37 of file ra8_gpt_regs.h.

Function Documentation

◆ ra8_gpt()

volatile r_gpt_channel_regs_t * ra8_gpt ( uint8_t channel )

inlinestatic

Data Structures