main.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_dmac.h"
#include "ra8_dmac_regs.h"
#include "ra8_err.h"
#include "ra8_isr.h"
#include "ra8_mstp.h"
#include "ra8_time.h"

typedef enum : uint32_t {
  k_dma_demo_baud       = 115200U, 
  k_dma_demo_period_ms  = 1000U,   
  k_dma_demo_buf_bytes  = 1024U,   
  k_dma_demo_buf_words  = 256U,    
  k_dma_demo_poll_limit = 100000U, 
} dma_demo_config_t;

typedef enum : uint8_t {
  k_dma_demo_channel = 0U, 
  k_dma_demo_byte_sh = 8U, 
} dma_demo_byte_t;

static const uint8_t s_dma_demo_ok_msg[]  = "dma: copied 1024B match=Y\r\n";
static const uint8_t s_dma_demo_bad_msg[] = "dma: copied 1024B match=N\r\n";

static uint32_t s_src[k_dma_demo_buf_words];
static uint32_t s_dst[k_dma_demo_buf_words];

RA8_INTERNAL static void internal_panic_halt(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

RA8_INTERNAL static void internal_setup_or_halt(void)
{
  uint32_t cpuclk0_hz = 0U;
 
  if (ra8_cgc_init() != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_cgc_get_clock_hz(k_ra8_clock_id_cpuclk0, &cpuclk0_hz) != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_mstp_init() != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_board_uart_console_init((uint32_t)k_dma_demo_baud) != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_board_led_init(k_ra8_board_led1) != k_ra8_ok) {
    internal_panic_halt();
  }
  if (ra8_board_led_init(k_ra8_board_led2) != k_ra8_ok) {
    internal_panic_halt();
  }
}

RA8_INTERNAL static void internal_fill_buffers(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_dma_demo_buf_words; ++i) {
    s_src[i] = i ^ (i >> (uint32_t)k_dma_demo_byte_sh);
    s_dst[i] = 0U;
  }
}

RA8_INTERNAL static uint8_t internal_verify(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_dma_demo_buf_words; ++i) {
    if (s_dst[i] != s_src[i]) {
      return 0U;
    }
  }
  return 1U;
}

[[nodiscard]] RA8_INTERNAL static ra8_err_t internal_run_copy(void)
{
  const ra8_dmac_config_t cfg = {
    .src         = (uint32_t)(uintptr_t)s_src,
    .dst         = (uint32_t)(uintptr_t)s_dst,
    .count       = (uint16_t)k_dma_demo_buf_words,
    .block_count = 1U,
    .width       = k_ra8_dmac_width_word,
    .src_inc     = true,
    .dst_inc     = true,
  };
  const ra8_err_t err = ra8_dmac_start_block((uint8_t)k_dma_demo_channel, &cfg);
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Software trigger: assert DMREQ.SWREQ on the channel.
   * HUM Ch 17.2.15 p 744: write SWREQ=1 to request one block-mode
   * transfer. SWREQ auto-clears when the controller accepts the
   * request (CLRS=0 is the reset default). */
  volatile r_dmac_channel_regs_t* reg = ra8_dmac((uint8_t)k_dma_demo_channel);
  if (reg == nullptr) {
    return k_ra8_err_hw_error;
  }
  reg->DMREQ = (uint8_t)k_ra8_dmreq_swreq_mask;
 
  /* Poll DMSTS.ACT until the controller goes idle.
   * HUM Ch 17.2.16 p 745: "When data transfer in response to one
   * transfer request is completed" the ACT flag clears. */
  for (uint32_t i = 0U; i < (uint32_t)k_dma_demo_poll_limit; ++i) {
    if ((reg->DMSTS & (uint8_t)k_ra8_dmsts_act_mask) == 0U) {
      return ra8_dmac_stop((uint8_t)k_dma_demo_channel);
    }
  }
  (void)ra8_dmac_stop((uint8_t)k_dma_demo_channel);
  return k_ra8_err_hw_timeout;
}
 
void main(void)
{
  internal_setup_or_halt();
  ra8_isr_globals_enable();
 
  while (1) {
    internal_fill_buffers();
    const ra8_err_t err = internal_run_copy();
    const uint8_t   ok  = (err == k_ra8_ok && internal_verify() != 0U) ? 1U : 0U;
    if (ok != 0U) {
      (void)ra8_board_uart_console_write(s_dma_demo_ok_msg,
                                         (size_t)(sizeof(s_dma_demo_ok_msg) - 1U));
      (void)ra8_board_led_toggle(k_ra8_board_led1);
    } else {
      (void)ra8_board_uart_console_write(s_dma_demo_bad_msg,
                                         (size_t)(sizeof(s_dma_demo_bad_msg) - 1U));
      (void)ra8_board_led_toggle(k_ra8_board_led2);
    }
    ra8_delay_ms(k_dma_demo_period_ms);
  }
  internal_panic_halt();
}