main.c File Reference

CPU0 (Cortex-M85) ping-pong demo against CPU1 (Cortex-M33). More...

#include <stdint.h>
#include "ra8_boot_entry.h"
#include "ra8_dual_core.h"
#include "ra8_err.h"
#include "shared_pingpong.h"

Include dependency graph for main.c:

Go to the source code of this file.

Enumerations
enum	cpu1_pingpong_err_sentinel_t : uint32_t { k_cpu1_pingpong_err_none = 0xFFFFFFFFU }
	Sentinel for g_cpu1_pingpong_release_err ("none yet"). More...

Functions
static RA8_INTERNAL bool	internal_wait_for_pong (const volatile cpu1_pingpong_shared_t *shared, uint32_t target)
	Poll until pong_seq reaches target or the budget runs out.
void	main (void)
	CPU0 application entry.

Variables
uint32_t	g_ra8_ls_cpu1_mram_start
uint32_t	g_ra8_ls_cpu1_stack_top
volatile uint32_t	g_cpu1_pingpong_match = 0U
	HIL liveness counter – incremented on every successful CPU0 -> CPU1 -> CPU0 ping/pong round-trip (got == 0x4321).
volatile uint32_t	g_cpu1_pingpong_mismatch = 0U
	HIL failure counter – incremented whenever a round-trip cannot complete: TX failed, RX timed out after the bounded poll, or the returned word was not the expected pong magic.
volatile uint32_t	g_cpu1_pingpong_step = 0U
	Boot progress tracker.
volatile uint32_t	g_cpu1_pingpong_release_err = k_cpu1_pingpong_err_none
	Captured ra8_cpu1_release return code.

Detailed Description

CPU0 (Cortex-M85) ping-pong demo against CPU1 (Cortex-M33).

Tag

[Ring 1 / app] {World: NS}

CPU0 side: releases CPU1 via ra8_cpu1_release, then exchanges ping/pong via a fixed shared-SRAM message struct (see shared_pingpong.h). The IPC peripheral is NOT used: this chip variant has SECEXT disabled on CPU1, IPC channel attribution (SAIPCIRn) is mutually exclusive S xor NS, and with CPU0 booting non-secure in this build neither core can flip a channel's attribution. Shared SRAM at 0x22100000 (the start of the upper on-chip SRAM region, below CPU1's 0x22190000 SRAM bank) sidesteps the IPC security problem entirely while still validating that CPU1 was released, booted, and is executing user code.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file main.c.

Enumeration Type Documentation

cpu1_pingpong_err_sentinel_t

enum cpu1_pingpong_err_sentinel_t : uint32_t

Sentinel for g_cpu1_pingpong_release_err ("none yet").

Enumerator
k_cpu1_pingpong_err_none	Cpu1 pingpong error none.

Definition at line 90 of file main.c.

Function Documentation

internal_wait_for_pong()

RA8_INTERNAL bool internal_wait_for_pong ( const volatile cpu1_pingpong_shared_t * shared, uint32_t target )

static

Poll until pong_seq reaches target or the budget runs out.

Re-reads the volatile response sequence up to the fixed iteration bound and returns immediately when CPU1 publishes the target.

Parameters

[in]	shared	Pointer to the shared message struct.
[in]	target	Sequence value to wait for.

Returns

Whether the wait observed the target.

Return values

true	pong_seq == target was observed inside the budget.
false	k_cpu1_pingpong_poll_budget iters elapsed first.

Precondition

shared != nullptr.

target equals the most recent value the caller wrote to ping_seq.

Postcondition

No shared state is mutated.

Iteration count bounded by k_cpu1_pingpong_poll_budget.

Note

Not thread-safe. CPU1 must already have been released or this always times out.

Since

0.1.0

Definition at line 117 of file main.c.

References k_cpu1_pingpong_poll_budget, cpu1_pingpong_shared_t::pong_seq, and RA8_INTERNAL.

main()

void main

(

void

)

CPU0 application entry.

The application entry point Reset_Handler hands control to.

See file header for behaviour summary.

Precondition

Boot init has completed.

CPU1 is held in reset.

Postcondition

CPU1 released and the ping-pong loop running.

Function never returns.

Note

Single-threaded entry.

Since

0.1.0

Definition at line 138 of file main.c.

References g_cpu1_pingpong_match, g_cpu1_pingpong_mismatch, g_cpu1_pingpong_release_err, g_cpu1_pingpong_step, g_ra8_ls_cpu1_mram_start, g_ra8_ls_cpu1_stack_top, internal_shared(), internal_wait_for_pong(), k_cpu1_pingpong_magic_ping, k_cpu1_pingpong_magic_pong, k_ra8_ok, cpu1_pingpong_shared_t::ping_payload, cpu1_pingpong_shared_t::ping_seq, cpu1_pingpong_shared_t::pong_payload, cpu1_pingpong_shared_t::pong_seq, and ra8_cpu1_release().

Variable Documentation

g_cpu1_pingpong_match

volatile uint32_t g_cpu1_pingpong_match = 0U

HIL liveness counter – incremented on every successful CPU0 -> CPU1 -> CPU0 ping/pong round-trip (got == 0x4321).

Read externally by scripts/hil/jlink_memprobe.sh via SWD. The probe asserts this counter advances by >= HIL_PROBE_MIN_ADVANCE over the sample window, proving CPU1 (Cortex-M33) was released, booted its vector table, and is servicing the IPC channel pair. If CPU1 never came out of reset, this counter stays at 0 – alive-mode could not catch that failure because CPU0 keeps iterating its outer loop.

Note

Read externally by J-Link only; firmware never reads back.

Since

0.1.0

Definition at line 51 of file main.c.

Referenced by main().

g_cpu1_pingpong_mismatch

volatile uint32_t g_cpu1_pingpong_mismatch = 0U

HIL failure counter – incremented whenever a round-trip cannot complete: TX failed, RX timed out after the bounded poll, or the returned word was not the expected pong magic.

The memprobe asserts this stays at 0 (or below HIL_PROBE_MAX_FAILURE). Catches "CPU1 hung after release", "IPC FIFO wedged", and "CPU1 echoed the wrong magic" – previously invisible because the outer while (1) happily continues on every failure.

Note

Read externally by J-Link only; firmware never reads back.

Since

0.1.0

Definition at line 69 of file main.c.

Referenced by main().

g_cpu1_pingpong_release_err

volatile uint32_t g_cpu1_pingpong_release_err = k_cpu1_pingpong_err_none

Captured ra8_cpu1_release return code.

Stamped right after the call returns so memprobe can read whichever ra8_err_t variant the HAL surfaced.

Since

0.1.0

Definition at line 94 of file main.c.

Referenced by main().

g_cpu1_pingpong_step

volatile uint32_t g_cpu1_pingpong_step = 0U

Boot progress tracker.

0 = pre-main; 1 = main() entry; 2 = after ra8_cpu1_release; 3 = after ra8_ipc_init; 4 = first loop iteration. Lets memprobe pinpoint exactly where CPU0 stalls.

Since

0.1.0

Definition at line 80 of file main.c.

Referenced by main().

g_ra8_ls_cpu1_mram_start

uint32_t g_ra8_ls_cpu1_mram_start

extern

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern