ra8_dual_core.c

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#include "ra8_dual_core.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"

static const char* const s_tag = "ra8_dual_core";

typedef enum : uint16_t {
  k_dc_byte_mask = 0xFFU, 
} dc_mask_t;
 
typedef enum : uint32_t {
  k_ra8_dual_core_align_vtor = 128U, 
  k_ra8_dual_core_align_sp   = 8U,   
} ra8_dual_core_align_t;
 
/* ----------------------------------------------------------------------------
 * Host shim
 * --------------------------------------------------------------------------*/
#ifdef RA8_OFF_TARGET

typedef struct {
  uint32_t initvtor; 
  uint16_t actcsr;   
  uint8_t  waitcr;   
} ra8_dual_core_fake_state_t;

static ra8_dual_core_fake_state_t s_fake = {
  .initvtor = 0U,
  .actcsr   = 0U,
  .waitcr   = 0U,
};

RA8_INTERNAL static inline uint16_t internal_actcsr_read(void)
{
  return s_fake.actcsr;
}

RA8_INTERNAL static inline void internal_actcsr_write(uint16_t value)
{
  const uint16_t key =
    (uint16_t)((value >> (uint16_t)k_ra8_dual_core_actcsr_key_shift) & k_dc_byte_mask);
  if (key != (uint16_t)k_ra8_dual_core_actcsr_key_value) {
    /* Only caller ra8_cpu1_release always presents KEY=0xA5; wrong-key drop is host-unreachable. */
    /* Silent drop -- matches HUM Ch 2.9.1.9 KEY gate. */
    return; /* GCOVR_EXCL_LINE -- build-fixed role */
  }
  uint16_t actcsr = s_fake.actcsr;
  if ((value & (uint16_t)k_ra8_dual_core_actcsr_actreq_mask) != 0U) {
    actcsr |= (uint16_t)k_ra8_dual_core_actcsr_act_mask;
  }
  s_fake.actcsr = actcsr;
}

RA8_INTERNAL static inline void internal_waitcr_write(uint8_t value)
{
  s_fake.waitcr = (uint8_t)(value & (uint8_t)k_ra8_dual_core_waitcr_cpuwait_mask);
}

RA8_INTERNAL static inline uint8_t internal_waitcr_read(void)
{
  return s_fake.waitcr;
}

RA8_INTERNAL static inline void internal_initvtor_write(uint32_t value)
{
  s_fake.initvtor = value;
}
 
#ifdef UNIT_TEST
volatile const void* ra8_dual_core_test_actcsr_key(void)
{
  return (volatile const void*)&s_fake.actcsr;
}
#endif /* UNIT_TEST */
 
#else /* !RA8_OFF_TARGET */

RA8_INTERNAL static inline volatile uint16_t* internal_actcsr_ptr(void)
{
  return (volatile uint16_t*)((uintptr_t)k_ra8_dual_core_ctrl_base_addr +
                              (uintptr_t)k_ra8_dual_core_off_cpu1_actcsr);
}

RA8_INTERNAL static inline volatile uint8_t* internal_waitcr_ptr(void)
{
  return (volatile uint8_t*)((uintptr_t)k_ra8_dual_core_ctrl_base_addr +
                             (uintptr_t)k_ra8_dual_core_off_cpu1_waitcr);
}

RA8_INTERNAL static inline volatile uint32_t* internal_initvtor_ptr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_dual_core_ctrl_base_addr +
                              (uintptr_t)k_ra8_dual_core_off_cpu1_initvtor);
}

RA8_INTERNAL static inline uint16_t internal_actcsr_read(void)
{
  return *internal_actcsr_ptr();
}

RA8_INTERNAL static inline void internal_actcsr_write(uint16_t value)
{
  *internal_actcsr_ptr() = value;
}

RA8_INTERNAL static inline void internal_waitcr_write(uint8_t value)
{
  *internal_waitcr_ptr() = value;
}

RA8_INTERNAL static inline uint8_t internal_waitcr_read(void)
{
  return *internal_waitcr_ptr();
}

RA8_INTERNAL static inline void internal_initvtor_write(uint32_t value)
{
  *internal_initvtor_ptr() = value;
}
 
#endif /* RA8_OFF_TARGET */

RA8_INTERNAL static inline bool internal_is_cpu0(void)
{
#ifdef RA8_BUILD_FOR_CPU1
  return false;
#else
  return true;
#endif
}

RA8_INTERNAL static ra8_err_t internal_wait_act_set(void)
{
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
  volatile const void* act_key = ra8_dual_core_test_actcsr_key();
#endif
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_dual_core_release_poll_max; ++i) {
    const bool act_set = (internal_actcsr_read() & (uint16_t)k_ra8_dual_core_actcsr_act_mask) != 0U;
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
    if (ra8_fake_mmio_wait_eval(act_key, i, act_set)) {
      return k_ra8_ok;
    }
#else
    if (act_set) {
      return k_ra8_ok;
    }
#endif
  }
  ra8_log_error(s_tag, "release: ACTCSR.ACT did not assert");
  return k_ra8_err_timeout;
}
 
/* ----------------------------------------------------------------------------
 * Public API
 * --------------------------------------------------------------------------*/

ra8_err_t ra8_cpu1_release(void* entry, void* sp)
{
  if (entry == nullptr || sp == nullptr) {
    ra8_log_error(s_tag, "release: NULL entry or sp");
    return k_ra8_err_null_ptr;
  }
  if (((uintptr_t)entry & ((uintptr_t)k_ra8_dual_core_align_vtor - 1U)) != 0U) {
    ra8_log_error(s_tag, "release: entry not 128-byte aligned");
    return k_ra8_err_invalid_arg;
  }
  if (((uintptr_t)sp & ((uintptr_t)k_ra8_dual_core_align_sp - 1U)) != 0U) {
    ra8_log_error(s_tag, "release: sp not 8-byte aligned");
    return k_ra8_err_invalid_arg;
  }
  if (!internal_is_cpu0()) {
    /* RA8_BUILD_FOR_CPU1 is never defined in host builds; this branch is compile-time dead. */
    ra8_log_error(s_tag, "release: caller is not CPU0"); /* GCOVR_EXCL_LINE -- build-fixed role */
    return k_ra8_err_not_supported;                      /* GCOVR_EXCL_LINE -- build-fixed role */
  }
 
  /* HUM Ch 2.9.1.7 "CPU1INITVTOR" p 128-129: program CPU1's initial
   * vector-table base. CPU1 will latch this into VTOR on the next
   * reset-release edge driven by ACTCSR.ACTREQ below. The M33 also
   * fetches its initial MSP from the first word of this table. */
  internal_initvtor_write((uint32_t)(uintptr_t)entry);
 
  /* HUM Ch 2.9.1.8 "CPU1WAITCR" p 129: make sure CPUWAIT is cleared so
   * CPU1 begins executing immediately on activation. Reset value is
   * already 0 but writing it defensively keeps repeated halt/release
   * cycles deterministic. */
  internal_waitcr_write(0U);
 
  /* HUM Ch 2.9.1.9 "CPU1ACTCSR" p 129-130: writes require KEY=0xA5 in
   * bits 15:8 alongside the ACTREQ bit. Anything else is silently
   * dropped by the hardware. */
  const uint16_t actreq = (uint16_t)(((uint16_t)k_ra8_dual_core_actcsr_key_value
                                      << (uint16_t)k_ra8_dual_core_actcsr_key_shift) |
                                     (uint16_t)k_ra8_dual_core_actcsr_actreq_mask);
  internal_actcsr_write(actreq);
 
  /* Bounded poll for ACT to assert (HUM Ch 2.9.1.9 ACT bit p 130). */
  return internal_wait_act_set();
}

ra8_err_t ra8_cpu1_halt(void)
{
  if (!internal_is_cpu0()) {
    /* RA8_BUILD_FOR_CPU1 is never defined in host builds; this branch is compile-time dead. */
    ra8_log_error(s_tag, "halt: caller is not CPU0"); /* GCOVR_EXCL_LINE -- build-fixed CPU role */
    return k_ra8_err_not_supported;                   /* GCOVR_EXCL_LINE -- build-fixed CPU role */
  }
 
  internal_waitcr_write((uint8_t)k_ra8_dual_core_waitcr_cpuwait_mask);
  return k_ra8_ok;
}

bool ra8_cpu1_is_running(void)
{
  /* Sequential ifs so the function has zero compound boolean
   * decisions -- keeps MC/DC test obligations linear per condition
   * rather than N+1 combinatorial, and matches the safety-checklist
   * preference for split conditions in libs/ra8_hal/. */
  const bool active = (internal_actcsr_read() & (uint16_t)k_ra8_dual_core_actcsr_act_mask) != 0U;
  if (!active) {
    return false;
  }
  const bool stalled =
    (internal_waitcr_read() & (uint8_t)k_ra8_dual_core_waitcr_cpuwait_mask) != 0U;
  return !stalled;
}