62typedef enum : uintptr_t {
72typedef enum : uint16_t {
87typedef enum : uint16_t {
99typedef enum : uint32_t {
174#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
196[[nodiscard]]
volatile const void* ra8_dual_core_test_actcsr_key(
void);
bool ra8_cpu1_is_running(void)
Return whether CPU1 is currently fetching instructions.
ra8_dual_core_const_t
Tunable constants for the bounded poll loops.
@ k_ra8_dual_core_release_poll_max
Bounded poll iterations.
ra8_err_t ra8_cpu1_release(void *entry, void *sp)
Release CPU1 (Cortex-M33) from reset and start it executing.
ra8_dual_core_field_t
Bit positions inside CPU1WAITCR / CPU1ACTCSR.
@ k_ra8_dual_core_actcsr_act_mask
CPU1ACTCSR.ACT.
@ k_ra8_dual_core_actcsr_actreq_mask
CPU1ACTCSR.ACTREQ.
@ k_ra8_dual_core_actcsr_key_shift
Key byte position.
@ k_ra8_dual_core_waitcr_cpuwait_mask
CPU1WAITCR.CPUWAIT.
@ k_ra8_dual_core_actcsr_key_value
Required key code.
ra8_dual_core_off_t
Offsets within the CPU_CTRL window for the CPU1 lifecycle registers (HUM Ch 2.9.1 p 128-130,...
@ k_ra8_dual_core_off_cpu1_actcsr
CPU1ACTCSR (16-bit).
@ k_ra8_dual_core_off_cpu1_waitcr
CPU1WAITCR (8-bit).
@ k_ra8_dual_core_off_cpu1_initvtor
CPU1INITVTOR (32-bit).
ra8_dual_core_addr_t
Base address of the CPU control register window used for secondary-core lifecycle management.
@ k_ra8_dual_core_ctrl_base_addr
CPU_CTRL Secure base.
ra8_err_t ra8_cpu1_halt(void)
Park CPU1 by asserting CPU1WAITCR.CPUWAIT.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.