ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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main.c
Go to the documentation of this file.
1
51
52#include <stddef.h>
53#include <stdint.h>
54
57#include "ra8_boot_entry.h"
58#include "ra8_cgc.h"
59#include "ra8_dual_core.h"
60#include "ra8_err.h"
61#include "ra8_log.h"
62
64extern uint32_t g_ra8_ls_cpu1_mram_start;
66extern uint32_t g_ra8_ls_cpu1_stack_top;
67
75typedef enum : uint32_t {
78
96volatile uint32_t g_cache_coherency_match = 0U;
97
113volatile uint32_t g_cache_coherency_mismatch = 0U;
114
126static const uint8_t s_cache_coherency_pass_banner[] = "cache_coherency_hil: 8 rounds PASS\r\n";
127
149{
150 if (ra8_cgc_init() != k_ra8_ok) {
151 return false;
152 }
154 return false;
155 }
156 return true;
157}
158
178{
180 (size_t)(sizeof(s_cache_coherency_pass_banner) - 1U));
182 ra8_log_info("M85", "cache_coherency_hil: 8 rounds PASS");
183}
184
201[[noreturn]] RA8_INTERNAL static void internal_park_forever(void)
202{
203 while (1) {
204 __asm volatile("nop");
205 }
206}
207
232 uint32_t target)
233{
234 if (shared == nullptr) {
235 return false;
236 }
237 for (uint32_t i = 0U; i < (uint32_t)k_cache_coherency_poll_budget; ++i) {
238 if (shared->pong_seq == target) {
239 return true;
240 }
241 }
242 return false;
243}
244
268RA8_INTERNAL static void
269internal_round(volatile cache_coherency_shared_t* shared, uint32_t round, uint32_t* next_seq)
270{
271 if ((shared == nullptr) || (next_seq == nullptr)) {
272 return;
273 }
274 const uint32_t expect = (uint32_t)k_cache_coherency_pong_base + round;
275
276 shared->ping_payload = (uint32_t)k_cache_coherency_ping_base + round;
277 __asm volatile("dsb" ::: "memory");
278 shared->ping_seq = *next_seq;
279
280 bool ok = internal_wait_for_pong(shared, *next_seq);
281 if (ok) {
282 ok = (shared->pong_payload == expect);
283 }
284 if (ok) {
286 } else {
288 }
289 *next_seq += 1U;
290}
291
303void main(void)
304{
305 ra8_log_init();
306 ra8_log_info("M85", "cache_coherency_hil: D-cache ON, non-cacheable shared SRAM");
307
308 volatile cache_coherency_shared_t* shared = internal_shared();
309 /* CPU0 owns initialisation of the shared block. Zero it before
310 * releasing CPU1 so CPU1 starts from a known clean state. */
311 shared->ping_seq = 0U;
312 shared->pong_seq = 0U;
313 shared->ping_payload = 0U;
314 shared->pong_payload = 0U;
315 __asm volatile("dsb" ::: "memory");
316
317 /* Best-effort VCOM console (banner) + LED1 (self-test heartbeat). */
318 const bool console_up = internal_console_init();
319 if (!console_up) {
320 ra8_log_info("M85", "VCOM console init failed -- banner over ITM only");
321 }
322 const bool led_up = (ra8_board_led_init(k_ra8_board_led1) == k_ra8_ok);
323
325 ra8_log_info_val("M85", "ra8_cpu1_release rc (0 = ok)", (uint32_t)err);
326 if (err != k_ra8_ok) {
327 ra8_log_info("M85", "release FAILED -- halting");
329 }
330
331 uint32_t next_seq = 1U;
332 uint32_t round = 0U;
333 bool banner_sent = false;
334
335 while (1) {
336 /* Self-test heartbeat: one IOPORT write per round keeps ra8_emulator's
337 * MMIO-keyed idle detector awake through the pure-SRAM hand-off so the
338 * banner surfaces under RA8_EMU_IDLE_STOP=1 (and the LED visibly
339 * blinks on the bench). Dropped once the self-test has passed, so the
340 * steady phase below is pure SRAM and IDLE_STOP can stop the fake. */
341 if (led_up && (round < (uint32_t)k_cache_coherency_rounds)) {
343 }
344
345 internal_round(shared, round, &next_seq);
346
347 if (!banner_sent && (g_cache_coherency_match >= (uint32_t)k_cache_coherency_rounds)) {
349 banner_sent = true;
350 }
351 round += 1U;
352 }
353}
void main(void)
Secure fallback main entry point.
Definition main.c:37
Shared-SRAM message layout for the M85<->M33 cache-coherency HIL test.
@ k_cache_coherency_poll_budget
Max spin iters per direction.
@ k_cache_coherency_rounds
Verified rounds before PASS.
@ k_cache_coherency_pong_base
Expected round-0 pong payload.
@ k_cache_coherency_ping_base
CPU0 round-0 ping payload.
static volatile cache_coherency_shared_t * internal_shared(void)
Typed pointer to the fixed-address shared message block.
uint32_t g_ra8_ls_cpu1_mram_start
cache_coherency_hil_const_t
VCOM-console line rate for the deterministic HIL banner.
Definition main.c:75
@ k_cache_coherency_hil_baud
VCOM console line rate (8N1).
Definition main.c:76
static RA8_INTERNAL void internal_round(volatile cache_coherency_shared_t *shared, uint32_t round, uint32_t *next_seq)
Run one cross-core round and update the HIL counters.
Definition main.c:269
volatile uint32_t g_cache_coherency_match
HIL liveness counter – incremented on every verified M85 -> M33 -> M85 round-trip (echo == pong_base ...
Definition main.c:96
volatile uint32_t g_cache_coherency_mismatch
HIL failure counter – incremented whenever a round cannot complete: the bounded pong wait timed out,...
Definition main.c:113
static const uint8_t s_cache_coherency_pass_banner[]
Deterministic HIL success banner (uart_scrape / emulator-scrape).
Definition main.c:126
static RA8_INTERNAL bool internal_wait_for_pong(const volatile cache_coherency_shared_t *shared, uint32_t target)
Poll until pong_seq reaches target or the budget runs out.
Definition main.c:231
uint32_t g_ra8_ls_cpu1_stack_top
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
ra8_err_t ra8_board_led_toggle(ra8_board_led_id_t led)
Toggle led's output state.
ra8_err_t ra8_board_led_init(ra8_board_led_id_t led)
Configure led as a digital output, initial level low (off).
@ k_ra8_board_led1
LED1, BLUE, P600 (jumper E27).
I/O-expander, USB, camera, external-memory, MIPI-DSI, UART console, and Ethernet portion of the EK-RA...
ra8_err_t ra8_board_uart_console_write(const uint8_t *data, size_t len)
Polled blocking write to the J-Link OB VCOM console.
ra8_err_t ra8_board_uart_console_init(uint32_t baud)
Configure SCI8 + PD02/PD03 as the debug-console UART.
ra8_err_t ra8_board_uart_console_flush(void)
Block until every byte queued on the J-Link OB VCOM console has finished clocking out on the wire.
Boot entry points shared between a vector table and its startup code.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Definition ra8_cgc.c:727
Dual-core (CPU0 / CPU1) lifecycle helper – public API.
ra8_err_t ra8_cpu1_release(void *entry, void *sp)
Release CPU1 (Cortex-M33) from reset and start it executing.
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
Lightweight Logging Interface for ra8-firmware.
void ra8_log_init(void)
Initialise the logging backend.
Definition ra8_log.c:379
#define ra8_log_info_val(tag, message, value)
RA8 log info val.
Definition ra8_log.h:366
#define ra8_log_info(tag, message)
RA8 log info.
Definition ra8_log.h:364
Cross-CPU message struct backed by a fixed non-cacheable SRAM address.
volatile uint32_t ping_payload
CPU0 writes ping_base + r, CPU1 reads.
volatile uint32_t ping_seq
CPU0 increments after writing payload.
volatile uint32_t pong_seq
CPU1 sets to match ping_seq after reply.
volatile uint32_t pong_payload
CPU1 writes ping_payload + delta.