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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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Cross-CPU message struct backed by a fixed non-cacheable SRAM address. More...
#include <cache_coherency_shared.h>
Data Fields | |
| volatile uint32_t | ping_seq |
| CPU0 increments after writing payload. | |
| volatile uint32_t | pong_seq |
| CPU1 sets to match ping_seq after reply. | |
| volatile uint32_t | ping_payload |
| CPU0 writes ping_base + r, CPU1 reads. | |
| volatile uint32_t | pong_payload |
| CPU1 writes ping_payload + delta. | |
Cross-CPU message struct backed by a fixed non-cacheable SRAM address.
Every field is volatile so the compiler emits a real memory access each loop iteration on both cores. The struct is small (16 bytes) and pinned at a 32-byte-aligned address, so with the M85 D-cache enabled it occupies a single cache line – except the MPU marks that line's region non-cacheable, so the accesses go straight to SRAM and stay coherent with the cacheless M33.
Definition at line 132 of file cache_coherency_shared.h.
| volatile uint32_t cache_coherency_shared_t::ping_payload |
CPU0 writes ping_base + r, CPU1 reads.
Definition at line 135 of file cache_coherency_shared.h.
Referenced by internal_cpu1_main(), internal_round(), and main().
| volatile uint32_t cache_coherency_shared_t::ping_seq |
CPU0 increments after writing payload.
Definition at line 133 of file cache_coherency_shared.h.
Referenced by internal_cpu1_main(), internal_round(), and main().
| volatile uint32_t cache_coherency_shared_t::pong_payload |
CPU1 writes ping_payload + delta.
Definition at line 136 of file cache_coherency_shared.h.
Referenced by internal_cpu1_main(), internal_round(), and main().
| volatile uint32_t cache_coherency_shared_t::pong_seq |
CPU1 sets to match ping_seq after reply.
Definition at line 134 of file cache_coherency_shared.h.
Referenced by internal_cpu1_main(), internal_wait_for_pong(), and main().