cache_coherency_shared.h

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#pragma once
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2_dualcore.h"
 
#ifdef __cplusplus
extern "C" {
#endif

typedef enum : uintptr_t {
  k_cache_coherency_shared_addr =
    (uintptr_t)k_ra8_board_shared_ram_base, 
} cache_coherency_addr_t;

typedef enum : uint32_t {
  k_cache_coherency_ping_base   = 0x1234U,   
  k_cache_coherency_pong_base   = 0x4321U,   
  k_cache_coherency_delta       = 0x30EDU,   
  k_cache_coherency_rounds      = 8UL,       
  k_cache_coherency_poll_budget = 2000000UL, 
  k_cache_coherency_align_bytes = 32UL,      
} cache_coherency_shared_const_t;
 
/* The data-carry invariant the two cores rely on: CPU1 adds the fixed
 * delta to the ping payload, and that must land exactly on the value
 * CPU0 expects (pong_base + r == (ping_base + r) + delta). */
static_assert((uint32_t)k_cache_coherency_ping_base + (uint32_t)k_cache_coherency_delta ==
                (uint32_t)k_cache_coherency_pong_base,
              "ping_base + delta must equal pong_base");
 
/* The shared struct must start on a 32-byte (cache-line) boundary so an
 * enabled D-cache never straddles it with adjacent cacheable data. The
 * fixed SRAM2 base is 1 MiB aligned, so this holds by construction. */
static_assert((uintptr_t)k_cache_coherency_shared_addr % (uintptr_t)k_cache_coherency_align_bytes ==
                0U,
              "shared block must be 32-byte (cache-line) aligned");

typedef struct {
  volatile uint32_t ping_seq;     
  volatile uint32_t pong_seq;     
  volatile uint32_t ping_payload; 
  volatile uint32_t pong_payload; 
} cache_coherency_shared_t;

RA8_INTERNAL static inline volatile cache_coherency_shared_t* internal_shared(void)
{
  return (volatile cache_coherency_shared_t*)(uintptr_t)k_cache_coherency_shared_addr;
}
 
#ifdef __cplusplus
}
#endif