86typedef enum : uintptr_t {
115typedef enum : uint32_t {
123 "the shared window must start below CPU1's private SRAM bank");
127 "the shared window must end exactly where CPU1's private bank begins");
ra8_board_dualcore_size_t
Lengths of the windows named by ra8_board_dualcore_addr_t.
@ k_ra8_board_cpu1_image_size_bytes
256 KiB MRAM window for the M33 image.
@ k_ra8_board_shared_ram_size_bytes
576 KiB, base up to CPU1's bank.
@ k_ra8_board_cpu1_sram_size_bytes
64 KiB CPU1 private bank.
ra8_board_dualcore_addr_t
Base addresses of the EK-RA8D2 dual-core memory map.
@ k_ra8_board_cpu1_image_base
MRAM_CPU1: where the linked M33 image is pinned, so one .hex spans both cores' code.
@ k_ra8_board_cpu1_sram_base
CPU1's private 64 KiB bank at the top of on-chip SRAM: .data, .bss and the M33 main stack.
@ k_ra8_board_shared_ram_base
Start of SRAM2: the CPU0 <-> CPU1 meeting window.
ra8_err_t ra8_board_shared_ram(ra8_board_shared_ram_t *out)
Describe the window where the M85 and the M33 meet.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Runtime descriptor of the CPU0 <-> CPU1 shared window.
bool non_cacheable
True when the boot MPU marks this window Normal non-cacheable, so a hand-off needs no clean or invali...
uint32_t size_bytes
Its length in bytes, bounded by CPU1's private bank.
void * base
Start of the shared window (k_ra8_board_shared_ram_base).