ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_board_ek_ra8d2_dualcore.h
Go to the documentation of this file.
1
51
52#pragma once
53
54#ifdef __cplusplus
55extern "C" {
56#endif
57
58#include <stdint.h>
59
60#include "ra8_err.h"
61
86typedef enum : uintptr_t {
97
121
122static_assert((uintptr_t)k_ra8_board_shared_ram_base < (uintptr_t)k_ra8_board_cpu1_sram_base,
123 "the shared window must start below CPU1's private SRAM bank");
124static_assert((uintptr_t)k_ra8_board_shared_ram_base +
127 "the shared window must end exactly where CPU1's private bank begins");
128
155typedef struct {
156 void* base;
157 uint32_t size_bytes;
165
203
204#ifdef __cplusplus
205}
206#endif
ra8_board_dualcore_size_t
Lengths of the windows named by ra8_board_dualcore_addr_t.
@ k_ra8_board_cpu1_image_size_bytes
256 KiB MRAM window for the M33 image.
@ k_ra8_board_shared_ram_size_bytes
576 KiB, base up to CPU1's bank.
@ k_ra8_board_cpu1_sram_size_bytes
64 KiB CPU1 private bank.
ra8_board_dualcore_addr_t
Base addresses of the EK-RA8D2 dual-core memory map.
@ k_ra8_board_cpu1_image_base
MRAM_CPU1: where the linked M33 image is pinned, so one .hex spans both cores' code.
@ k_ra8_board_cpu1_sram_base
CPU1's private 64 KiB bank at the top of on-chip SRAM: .data, .bss and the M33 main stack.
@ k_ra8_board_shared_ram_base
Start of SRAM2: the CPU0 <-> CPU1 meeting window.
ra8_err_t ra8_board_shared_ram(ra8_board_shared_ram_t *out)
Describe the window where the M85 and the M33 meet.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
Runtime descriptor of the CPU0 <-> CPU1 shared window.
bool non_cacheable
True when the boot MPU marks this window Normal non-cacheable, so a hand-off needs no clean or invali...
uint32_t size_bytes
Its length in bytes, bounded by CPU1's private bank.
void * base
Start of the shared window (k_ra8_board_shared_ram_base).