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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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Runtime descriptor of the CPU0 <-> CPU1 shared window. More...
#include <ra8_board_ek_ra8d2_dualcore.h>
Data Fields | |
| void * | base |
| Start of the shared window (k_ra8_board_shared_ram_base). | |
| uint32_t | size_bytes |
| Its length in bytes, bounded by CPU1's private bank. | |
| bool | non_cacheable |
| True when the boot MPU marks this window Normal non-cacheable, so a hand-off needs no clean or invalidate. | |
Runtime descriptor of the CPU0 <-> CPU1 shared window.
What ra8_board_shared_ram fills in. An application carves its mailbox out of base rather than out of a literal it copied, and a memory-map change becomes one edit here plus a rebuild.
Definition at line 155 of file ra8_board_ek_ra8d2_dualcore.h.
| void* ra8_board_shared_ram_t::base |
Start of the shared window (k_ra8_board_shared_ram_base).
Definition at line 156 of file ra8_board_ek_ra8d2_dualcore.h.
| bool ra8_board_shared_ram_t::non_cacheable |
True when the boot MPU marks this window Normal non-cacheable, so a hand-off needs no clean or invalidate.
False in a build without RA8_BOOT_ENABLE_CACHE_MPU – where the M85 D-cache is not enabled either, so nothing is stale, but the memory map itself makes no promise.
Definition at line 158 of file ra8_board_ek_ra8d2_dualcore.h.
| uint32_t ra8_board_shared_ram_t::size_bytes |
Its length in bytes, bounded by CPU1's private bank.
Definition at line 157 of file ra8_board_ek_ra8d2_dualcore.h.