main.c File Reference

CPU0 (Cortex-M85 primary core) launcher for the M33 blink template. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2_peripherals.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_dual_core.h"
#include "ra8_err.h"
#include "ra8_log.h"

Include dependency graph for main.c:

Go to the source code of this file.

Enumerations
enum	blink_m33_hil_t : uint32_t { k_blink_m33_hil_baud = 115200U }
	VCOM-console line rate for the deterministic HIL success banner. More...

Functions
static bool	internal_console_init (void)
	Bring up the SCI8 / J-Link OB VCOM console for the HIL success banner.
static void	internal_emit_pass (void)
	Emit the deterministic HIL success banner over the VCOM console.
static void	internal_park_forever (void)
	Park the M85 forever after an unrecoverable startup failure.
static void	internal_idle_forever (void)
	Idle the M85 forever once the M33 owns the work (low-power posture).
void	main (void)
	CPU0 (Cortex-M85) application entry.

Variables
uint32_t	g_ra8_ls_cpu1_mram_start
	Base of the embedded M33 image / its vector table (MRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_stack_top
	Initial stack pointer handed to the M33 at release.
static const uint8_t	s_blink_m33_pass_banner [] = "blink_m33: m33 released PASS\r\n"
	Deterministic HIL banner: the M33 secondary core was released (uart_scrape).

Detailed Description

CPU0 (Cortex-M85 primary core) launcher for the M33 blink template.

Tag

[Ring 1 / app] {World: S}

This is the firmware that runs on the RA8D2's primary core, the Cortex-M85, out of reset. It is the canonical "target the M33" template (issue #152): the M85 does the minimum – release the secondary Cortex-M33 and then sleep – and the M33 owns the work. Here the work is blinking LED1, but any portable app drops into cpu1_main.c the same way.

1. Two images, one per core. This M85 ELF carries an embedded Cortex-M33 image (.cpu1_image, built from cpu1_main.c by the shared ra8_add_cpu1_image() recipe). One .hex flashes both cores.
2. The co-processor / low-power model. The M85 releases the M33 with ra8_cpu1_release (HUM Ch 2.9.1 "CPU control registers"), then drops into a WFI idle loop. With the heavy M85 asleep and the lean M33 doing the work, this is the low-power posture issue #150 builds on.

Everything the M85 does is logged with ra8_log, which the emulator echoes as [itm] lines (the J-Link SWO trace analog). The M33's proof-of-life is the blinking LED the M85 never drives. See README.md.

Note

ra8_log_info is compiled to a no-op unless the build defines a log level of INFO or finer (a Debug build). just apps::emulator::run blink_m33 builds Debug so the [itm] lines appear.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file main.c.

Enumeration Type Documentation

blink_m33_hil_t

enum blink_m33_hil_t : uint32_t

VCOM-console line rate for the deterministic HIL success banner.

The EK-RA8D2 J-Link OB VCOM bridge (SCI8, PD02/PD03) runs 8N1 at this rate; the Pi HIL rig's uart_scrape reads /dev/ttyACM0 to gate the app. The banner is additive to the existing ra8_log ITM trace.

Since

0.1.0

Enumerator
k_blink_m33_hil_baud	VCOM console line rate (8N1).

Definition at line 61 of file main.c.

Function Documentation

internal_console_init()

bool internal_console_init ( void )

static

Bring up the SCI8 / J-Link OB VCOM console for the HIL success banner.

Configures the clock tree (ra8_cgc_init, which publishes the PCLKA the SCI8 BRR divisor is computed from – and which the released M33 then shares) then the EK-RA8D2 debug console (ra8_board_uart_console_init, SCI8 on PD02/PD03 at k_blink_m33_hil_baud). Best-effort: a failure only means the additive HIL banner cannot reach the host; the existing ra8_log ITM trace and the M33 release are unaffected.

Returns

Whether the VCOM console is ready to carry the banner.

Return values

true	Clock + SCI8 console are up.
false	A bring-up step failed (the banner is then silently skipped).

Precondition

Called once during M85 bring-up, before ra8_cpu1_release.

ra8_log_init has run (failures are narrated over ITM).

Postcondition

On true, SCI8 is enabled (TE/RE) and PD02/PD03 route to it.

On false, no console state persists; the app continues normally.

Note

Not thread-safe; single-threaded boot context.

Since

0.1.0

Definition at line 103 of file main.c.

References k_blink_m33_hil_baud, k_ra8_ok, ra8_board_uart_console_init(), ra8_cgc_init(), and RA8_INTERNAL.

Referenced by main().

internal_emit_pass()

void internal_emit_pass ( void )

static

Emit the deterministic HIL success banner over the VCOM console.

Writes s_blink_m33_pass_banner to the SCI8 / J-Link OB VCOM console and flushes it so the bytes clock out before the M85 parks in WFI. A no-op if the console never came up (the write returns k_ra8_err_not_initialized, ignored).

Returns

Nothing.

Precondition

Reached only after ra8_cpu1_release returned k_ra8_ok (single guard).

internal_console_init was attempted during bring-up.

Postcondition

The banner has been handed to SCI8 and the TX FIFO drained (if up).

No M33 / mailbox state is modified.

Note

Not thread-safe; single-threaded boot context.

Since

0.1.0

Definition at line 132 of file main.c.

References ra8_board_uart_console_flush(), ra8_board_uart_console_write(), RA8_INTERNAL, and s_blink_m33_pass_banner.

Referenced by main().

internal_idle_forever()

void internal_idle_forever ( void )

static

Idle the M85 forever once the M33 owns the work (low-power posture).

After releasing the M33 the M85 has nothing to do, so it sleeps in a WFI loop. Modelling the heavy core asleep while the lean M33 runs is the low-power co-processor posture this template exists to demonstrate.

Returns

This function never returns.

Note

The core stays asleep between interrupts.

Precondition

The M33 has been released successfully.

No further M85-side work is pending.

Postcondition

The M85 consumes minimal power between wake events.

The M33 continues blinking independently.

Note

WFI wakes on any pending interrupt; this template enables none, so the M85 simply stays asleep.

Since

0.1.0

Definition at line 182 of file main.c.

References RA8_INTERNAL.

Referenced by main().

internal_park_forever()

void internal_park_forever ( void )

static

Park the M85 forever after an unrecoverable startup failure.

Reached only if ra8_cpu1_release fails, so the M33 never started. The core spins with the failure already logged.

Returns

This function never returns.

Note

The core spins in place.

Precondition

A fatal error (CPU1 release failure) has occurred.

The failure has already been logged.

Postcondition

The M85 makes no further forward progress.

The M33 stays held in reset.

Note

Mirrors the M33's fault handler for symmetry.

Since

0.1.0

Definition at line 156 of file main.c.

References RA8_INTERNAL.

Referenced by main().

main()

void main

(

void

)

CPU0 (Cortex-M85) application entry.

The application entry point Reset_Handler hands control to.

Brings up logging, releases the Cortex-M33 (which then blinks LED1), and idles. See the file header for the teaching narrative.

Precondition

SystemInit has completed core bring-up.

The M33 is held in reset by hardware until released here.

Postcondition

The M33 has been released and is blinking LED1.

This function never returns to its caller.

Note

Single-threaded; no RTOS on the M85 in this template.

Since

0.1.0

Definition at line 203 of file main.c.

References g_ra8_ls_cpu1_mram_start, g_ra8_ls_cpu1_stack_top, internal_console_init(), internal_emit_pass(), internal_idle_forever(), internal_park_forever(), k_ra8_ok, ra8_cpu1_release(), ra8_log_info, ra8_log_info_val, and ra8_log_init().

Variable Documentation

g_ra8_ls_cpu1_mram_start

uint32_t g_ra8_ls_cpu1_mram_start

extern

Base of the embedded M33 image / its vector table (MRAM_CPU1).

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern

Initial stack pointer handed to the M33 at release.

s_blink_m33_pass_banner

const uint8_t s_blink_m33_pass_banner[] = "blink_m33: m33 released PASS\r\n"

static

Deterministic HIL banner: the M33 secondary core was released (uart_scrape).

This template has no shared-SRAM mailbox – the M33's proof-of-life is the LED1 blink the M85 never drives. The strongest verdict the M85 can report over VCOM is that ra8_cpu1_release succeeded; the operator (or the bench rig) confirms the blink visually. Emitted only on the success path, additive to the existing ra8_log ITM trace, so the Pi rig (which has no SWO / ITM capture) can gate the boot + release path.

Note

Trailing CRLF terminates the line on the wire; the gate matches the text.

Warning

Do not modify; the HIL gate (hil.conf HIL_EXPECT) matches it exactly.

Since

0.1.0

Definition at line 78 of file main.c.

Referenced by internal_emit_pass().