cpu1_main.c File Reference

CPU1 (Cortex-M33) ping-pong responder. More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_err.h"
#include "ra8_ipc.h"

Include dependency graph for cpu1_main.c:

Go to the source code of this file.

Enumerations
enum	cpu1_main_const_t : uint32_t {   k_cpu1_pingpong_magic_ping = 0x1234U ,   k_cpu1_pingpong_magic_pong = 0x4321U }
enum	cpu1_main_pair_t : uint8_t { k_cpu1_pingpong_pair_zero = 0U }
enum	cpu1_ipc_addr_t : uintptr_t {   k_cpu1_ipc_ch0_addr = 0x500200C0UL ,   k_cpu1_ipc_ch2_addr = 0x50020100UL }
enum	cpu1_ipc_off_t : uint8_t {   k_cpu1_ipc_off_sta = 0x00U ,   k_cpu1_ipc_off_txd = 0x08U ,   k_cpu1_ipc_off_rxd = 0x0CU ,   k_cpu1_ipc_off_clr = 0x10U }
enum	cpu1_ipc_mask_t : uint32_t {   k_cpu1_ipc_sta_rdy = 0x00010000UL ,   k_cpu1_ipc_clr_all = 0x030100FFUL }
enum	cpu1_sau_reg_t : uintptr_t {   k_cpu1_sau_ctrl_addr = 0xE000EDD0UL ,   k_cpu1_sau_rnr_addr = 0xE000EDD8UL ,   k_cpu1_sau_rbar_addr = 0xE000EDDCUL ,   k_cpu1_sau_rlar_addr = 0xE000EDE0UL }
	Armv8-M SAU programming registers, addressed directly. More...
enum	cpu1_sau_region_t : uint32_t {   k_cpu1_sau_periph_ns_base = 0x50000000UL ,   k_cpu1_sau_periph_ns_limit = 0x5FFFFFE1UL ,   k_cpu1_sau_periph_s_base = 0x40000000UL ,   k_cpu1_sau_periph_s_limit = 0x4FFFFFE1UL ,   k_cpu1_sau_ns_sram_base = 0x22100000UL ,   k_cpu1_sau_ns_sram_limit = 0x221FFFE1UL ,   k_cpu1_sau_mram_base = 0x020C0000UL ,   k_cpu1_sau_mram_limit = 0x020FFFE1UL }
	Base and limit words for the four SAU regions this image programmes. More...
enum	cpu1_probe_addr_t : uintptr_t {   k_cpu1_probe_reset_addr = 0x32100200UL ,   k_cpu1_probe_data_addr = 0x32100204UL ,   k_cpu1_probe_bss_addr = 0x32100208UL ,   k_cpu1_probe_main_addr = 0x3210020CUL ,   k_cpu1_probe_sau_addr = 0x32100214UL ,   k_cpu1_probe_iter_addr = 0x32100220UL ,   k_cpu1_probe_rxd_addr = 0x32100224UL ,   k_cpu1_probe_pong_addr = 0x32100228UL ,   k_cpu1_probe_preread_addr = 0x32100230UL ,   k_cpu1_probe_sta_addr = 0x32100234UL ,   k_cpu1_probe_sem_addr = 0x32100238UL ,   k_cpu1_probe_reset_s_addr = 0x22190200UL ,   k_cpu1_ipcsem0_ns_addr = 0x50020000UL }
	Bench probe words this image writes for a J-Link post-mortem. More...
enum	cpu1_probe_val_t : uint32_t {   k_cpu1_probe_reset_val = 0xC0DEDEADUL ,   k_cpu1_probe_data_val = 0xB055A55AUL ,   k_cpu1_probe_bss_val = 0xBEEFCAFEUL ,   k_cpu1_probe_main_val = 0x11111111UL ,   k_cpu1_probe_sau_val = 0x33333333UL ,   k_cpu1_probe_pre_val = 0xAAAAAAAAUL }
	Sentinel values written to the cpu1_probe_addr_t probe words. More...

Functions
void	cpu1_reset_handler (void)
	CPU1 reset handler.
static void	internal_cpu1_sau_init (void)
	Programme CPU1's SAU and enable it.
static void	internal_cpu1_main (void)
	Run the CPU1 side of the ping-pong exchange.
static void	internal_cpu1_fault_handler (void)
	Default fault handler.

Variables
uint32_t	g_ra8_ls_cpu1_stack_top
uint32_t	g_ra8_ls_cpu1_data_start
uint32_t	g_ra8_ls_cpu1_data_end
uint32_t	g_ra8_ls_cpu1_data_load
uint32_t	g_ra8_ls_cpu1_bss_start
uint32_t	g_ra8_ls_cpu1_bss_end
const uintptr_t	g_cpu1_vector_table []
	Minimal Armv8-M vector table for CPU1.

Detailed Description

CPU1 (Cortex-M33) ping-pong responder.

Tag

[Ring 1 / app] {World: NS}

Built as a separate ELF (-mcpu=cortex-m33). Receives 0x1234 on the CPU0 -> CPU1 channel and replies with 0x4321 in a loop.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file cpu1_main.c.

Enumeration Type Documentation

cpu1_ipc_addr_t

enum cpu1_ipc_addr_t : uintptr_t

Enumerator
k_cpu1_ipc_ch0_addr	CPU1 TX to CPU0 (NS alias).
k_cpu1_ipc_ch2_addr	CPU1 RX from CPU0 (NS alias).

Definition at line 44 of file cpu1_main.c.

cpu1_ipc_mask_t

enum cpu1_ipc_mask_t : uint32_t

Enumerator
k_cpu1_ipc_sta_rdy	Cpu1 ipc sta rdy.
k_cpu1_ipc_clr_all	Cpu1 ipc clr all.

Definition at line 56 of file cpu1_main.c.

cpu1_ipc_off_t

enum cpu1_ipc_off_t : uint8_t

Enumerator
k_cpu1_ipc_off_sta	Cpu1 ipc off sta.
k_cpu1_ipc_off_txd	Cpu1 ipc off txd.
k_cpu1_ipc_off_rxd	Cpu1 ipc off rxd.
k_cpu1_ipc_off_clr	Cpu1 ipc off clr.

Definition at line 49 of file cpu1_main.c.

cpu1_main_const_t

enum cpu1_main_const_t : uint32_t

Enumerator
k_cpu1_pingpong_magic_ping	Cpu1 pingpong magic ping.
k_cpu1_pingpong_magic_pong	Cpu1 pingpong magic pong.

Definition at line 31 of file cpu1_main.c.

cpu1_main_pair_t

enum cpu1_main_pair_t : uint8_t

Enumerator
k_cpu1_pingpong_pair_zero	Cpu1 pingpong pair zero.

Definition at line 36 of file cpu1_main.c.

cpu1_probe_addr_t

enum cpu1_probe_addr_t : uintptr_t

Bench probe words this image writes for a J-Link post-mortem.

CPU1 is a permanent-NS controller, so it reaches shared SRAM through the NS alias at 0x321.....; CPU0's J-Link memprobe sees the same backing store through the standard view. Each word marks one point in the boot and IPC sequence having been reached.

Invariant

Every address lies inside an SAU region this image programmes NS.

See also

cpu1_probe_val_t The sentinel values written to them.

Enumerator
k_cpu1_probe_reset_addr	Reset entry.
k_cpu1_probe_data_addr	Data copied.
k_cpu1_probe_bss_addr	BSS cleared.
k_cpu1_probe_main_addr	Main entry.
k_cpu1_probe_sau_addr	SAU ready.
k_cpu1_probe_iter_addr	Loop count.
k_cpu1_probe_rxd_addr	Last RX word.
k_cpu1_probe_pong_addr	Pong count.
k_cpu1_probe_preread_addr	Pre-read mark.
k_cpu1_probe_sta_addr	CH2 status.
k_cpu1_probe_sem_addr	Semaphore.
k_cpu1_probe_reset_s_addr	SRAM reset mark.
k_cpu1_ipcsem0_ns_addr	NS semaphore.

Definition at line 110 of file cpu1_main.c.

cpu1_probe_val_t

enum cpu1_probe_val_t : uint32_t

Sentinel values written to the cpu1_probe_addr_t probe words.

Each is visually distinct in a memory dump so a bench operator can tell how far the image progressed from the raw hex alone.

Invariant

No value is a plausible uninitialised-SRAM pattern.

See also

cpu1_probe_addr_t The addresses these are written to.

Enumerator
k_cpu1_probe_reset_val	Reset entry.
k_cpu1_probe_data_val	Data copied.
k_cpu1_probe_bss_val	BSS cleared.
k_cpu1_probe_main_val	Main entry.
k_cpu1_probe_sau_val	SAU ready.
k_cpu1_probe_pre_val	Pre-read.

Definition at line 134 of file cpu1_main.c.

cpu1_sau_reg_t

enum cpu1_sau_reg_t : uintptr_t

Armv8-M SAU programming registers, addressed directly.

These are Cortex-M33 CPU-architectural registers (Arm v8-M Architecture Reference Manual, "SAU registers"), not RA8D2 peripheral registers, so they carry an Arm ARM reference rather than a HUM citation. The M33 HAL accessors are unreachable from this image, hence the direct addresses.

Invariant

Every value is a word-aligned address inside the System Control Space at 0xE000E000.

See also

cpu1_sau_region_t The region base/limit values written through them.

Enumerator
k_cpu1_sau_ctrl_addr	SAU_CTRL: SAU enable bit.
k_cpu1_sau_rnr_addr	SAU_RNR: region number select.
k_cpu1_sau_rbar_addr	SAU_RBAR: region base address.
k_cpu1_sau_rlar_addr	SAU_RLAR: region limit + enable.

Definition at line 73 of file cpu1_main.c.

cpu1_sau_region_t

enum cpu1_sau_region_t : uint32_t

Base and limit words for the four SAU regions this image programmes.

Each limit value carries the SAU_RLAR ENABLE bit (bit 0) already set, which is why every limit ends in 1 rather than 0.

Invariant

The four regions do not overlap: overlapping SAU regions resolve to Secure, which a permanent-NS M33 cannot reach.

See also

cpu1_sau_reg_t The registers these are written to.

Enumerator
k_cpu1_sau_periph_ns_base	R0 NS base.
k_cpu1_sau_periph_ns_limit	R0 limit.
k_cpu1_sau_periph_s_base	R1 S base.
k_cpu1_sau_periph_s_limit	R1 limit.
k_cpu1_sau_ns_sram_base	R2 SRAM base.
k_cpu1_sau_ns_sram_limit	R2 limit.
k_cpu1_sau_mram_base	R3 MRAM base.
k_cpu1_sau_mram_limit	R3 limit.

Definition at line 89 of file cpu1_main.c.

Function Documentation

cpu1_reset_handler()

void cpu1_reset_handler

(

void

)

CPU1 reset handler.

CPU1 reset handler: minimal C-runtime init, then enter the hold loop.

CPU1 reset handler: minimal C-runtime init, then run the reader.

CPU1 reset handler: minimal C-runtime init, then run the emitter.

CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.

Runs the minimal C-runtime init the M33 image needs before branching into internal_cpu1_main:

1. Copy .data from its MRAM_CPU1 load image into SRAM_CPU1.
2. Zero .bss in SRAM_CPU1.

Without these passes the CPU1 image's globals (e.g. the s_ipc_channels array in ra8_ipc.c – .bss – and any initialised file-scope statics – .data) hold whatever pattern SRAM_CPU1 contained at boot. That was the reason CPU1 silently stayed wedged after Agent D embedded the CPU1 binary: the M33 jumped straight into internal_cpu1_main with uninitialised globals, so ra8_ipc_init / ra8_ipc_recv_message operated on garbage state structures and the channel pair never came alive.

Precondition

Initial SP loaded by hardware from the first slot of .cpu1_vectors (= g_ra8_ls_cpu1_stack_top).

CPU1 has just exited reset via the ACTREQ handshake driven by ra8_cpu1_release on CPU0.

Postcondition

.data mirrors the MRAM_CPU1 load image.

.bss is zero-filled.

Never returns; internal_cpu1_main enters its infinite IPC loop.

Note

Called only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss before any C code runs; the linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_main, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

The M33 boots with uninitialised RAM, so before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_run_compile, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

The M33 boots with uninitialised RAM, so before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols. The SDRAM framebuffer is in a NOLOAD section and is painted by ra8_gfx_clear, so it is deliberately left out of this init.

Returns

This function never returns.

Note

Control passes to cpu1_run_reader, which holds forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

The M33 boots with uninitialised RAM, so before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_hold_page, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

The M33 boots with uninitialised RAM, so before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_main, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Runs the minimal C-runtime init the M33 image needs before branching into cpu1_main:

1. Copy .data from its MRAM_CPU1 load image into SRAM_CPU1.
2. Zero .bss in SRAM_CPU1.

Precondition

Initial SP loaded by hardware from the first slot of .cpu1_vectors (= g_ra8_ls_cpu1_stack_top).

CPU1 has just exited reset via the ACTREQ handshake driven by ra8_cpu1_release on CPU0.

Postcondition

.data mirrors the MRAM_CPU1 load image.

.bss is zero-filled.

Never returns; cpu1_main enters its responder loop.

Note

Called only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Runs the minimal C-runtime init the M33 image needs before branching into internal_cpu1_main:

1. Copy .data from its MRAM_CPU1 load image into SRAM_CPU1.
2. Zero .bss in SRAM_CPU1.

Without these passes the CPU1 image's globals (e.g. the s_ipc_channels array in ra8_ipc.c – .bss – and any initialised file-scope statics – .data) hold whatever pattern SRAM_CPU1 contained at boot. That was the reason CPU1 silently stayed wedged after Agent D embedded the CPU1 binary: the M33 jumped straight into internal_cpu1_main with uninitialised globals, so ra8_ipc_init / ra8_ipc_recv_message operated on garbage state structures and the channel pair never came alive.

Precondition

Initial SP loaded by hardware from the first slot of .cpu1_vectors (= g_ra8_ls_cpu1_stack_top).

CPU1 has just exited reset via the ACTREQ handshake driven by ra8_cpu1_release on CPU0.

Postcondition

.data mirrors the MRAM_CPU1 load image.

.bss is zero-filled.

Never returns; internal_cpu1_main enters its infinite shared-SRAM loop.

Note

Called only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

The M33 boots with uninitialised RAM. Before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_main, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

The M33 boots with uninitialised RAM, so before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. Skipping this leaves file-scope globals holding whatever pattern SRAM held at power-on. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_main, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Definition at line 266 of file cpu1_main.c.

References g_ra8_ls_cpu1_bss_end, g_ra8_ls_cpu1_bss_start, g_ra8_ls_cpu1_data_end, g_ra8_ls_cpu1_data_load, g_ra8_ls_cpu1_data_start, internal_cpu1_main(), k_cpu1_probe_bss_addr, k_cpu1_probe_bss_val, k_cpu1_probe_data_addr, k_cpu1_probe_data_val, k_cpu1_probe_reset_addr, k_cpu1_probe_reset_s_addr, and k_cpu1_probe_reset_val.

internal_cpu1_fault_handler()

void internal_cpu1_fault_handler ( void )

static

Default fault handler.

All M33 exception slots route here.

Precondition

Hardware fault occurred.

Caller is the M33 exception entry path.

Postcondition

CPU1 stops making forward progress.

Watchdog (if enabled) eventually resets the chip.

Note

Used as default for all exception slots.

Since

0.1.0

Definition at line 318 of file cpu1_main.c.

References RA8_INTERNAL.

internal_cpu1_main()

void internal_cpu1_main ( void )

static

Run the CPU1 side of the ping-pong exchange.

Marks entry for the hardware probe, configures CPU1's SAU, polls channel 2 for the ping word, and writes the pong word to channel 0. Unexpected words are discarded and polling resumes.

Precondition

The reset handler has copied .data and cleared .bss.

CPU1 owns channel 2 as receiver and channel 0 as transmitter.

Postcondition

Never returns; a valid ping increments the pong probe counter.

The latest semaphore, status, and received-word probes remain visible.

Note

Single-threaded CPU1 entry; the peer owns the opposite FIFO endpoints.

Since

0.1.0

Definition at line 204 of file cpu1_main.c.

References internal_cpu1_sau_init(), k_cpu1_ipc_ch0_addr, k_cpu1_ipc_ch2_addr, k_cpu1_ipc_off_rxd, k_cpu1_ipc_off_sta, k_cpu1_ipc_off_txd, k_cpu1_ipc_sta_rdy, k_cpu1_ipcsem0_ns_addr, k_cpu1_pingpong_magic_ping, k_cpu1_pingpong_magic_pong, k_cpu1_probe_iter_addr, k_cpu1_probe_main_addr, k_cpu1_probe_main_val, k_cpu1_probe_pong_addr, k_cpu1_probe_pre_val, k_cpu1_probe_preread_addr, k_cpu1_probe_rxd_addr, k_cpu1_probe_sem_addr, k_cpu1_probe_sta_addr, and RA8_INTERNAL.

Referenced by cpu1_reset_handler().

internal_cpu1_sau_init()

void internal_cpu1_sau_init ( void )

static

Programme CPU1's SAU and enable it.

CPU1's M33 has its own SAU with 8 regions (SAU_TYPE.SREGION=8). Out of reset SAU is disabled and the IDAU default treats bit-28-clear as Secure. This programmes explicit NS regions for the peripheral window, the NS SRAM (which now also holds the CPU1 SRAM bank), and the CPU1 MRAM image, then enables the SAU.

Precondition

Called from internal_cpu1_main before any NS peripheral or IPC access.

The M33 is still running with its reset-default SAU (disabled).

Postcondition

Regions 0-3 are programmed and SAU_CTRL.ENABLE is set.

k_cpu1_probe_sau_addr holds k_cpu1_probe_sau_val, so a bench post-mortem can tell this stage completed.

Note

Not thread-safe; single-threaded boot context by construction.

Warning

Overlapping SAU regions resolve to Secure, which the permanent-NS M33 cannot reach – which is why one region covers both the shared markers and the CPU1 bank rather than two overlapping ones.

Since

0.1.0

Definition at line 162 of file cpu1_main.c.

References k_cpu1_probe_sau_addr, k_cpu1_probe_sau_val, k_cpu1_sau_ctrl_addr, k_cpu1_sau_mram_base, k_cpu1_sau_mram_limit, k_cpu1_sau_ns_sram_base, k_cpu1_sau_ns_sram_limit, k_cpu1_sau_periph_ns_base, k_cpu1_sau_periph_ns_limit, k_cpu1_sau_periph_s_base, k_cpu1_sau_periph_s_limit, k_cpu1_sau_rbar_addr, k_cpu1_sau_rlar_addr, k_cpu1_sau_rnr_addr, and RA8_INTERNAL.

Referenced by internal_cpu1_main().

Variable Documentation

g_cpu1_vector_table

const uintptr_t g_cpu1_vector_table[]

Initial value:

                                     = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
}

Minimal Armv8-M vector table for CPU1.

Minimal Armv8-M (baseline) vector table for the M33 image.

Initial-SP slot overridden by SYSC.MSPC1 at release.

Note

Placed in .cpu1_vectors by the linker.

Warning

Do not modify at runtime.

Since

0.1.0

Slot 0 is the initial SP, slot 1 the reset handler; the remaining core-exception slots share the fault handler. The M85 points CPU1INITVTOR at this table when it releases the core.

Note

Placed in the .cpu1_vectors section by linker_script_cpu1.ld.

Warning

Do not modify at runtime.

Since

0.1.0

Definition at line 337 of file cpu1_main.c.

g_ra8_ls_cpu1_bss_end

uint32_t g_ra8_ls_cpu1_bss_end

extern

Referenced by cpu1_reset_handler().

g_ra8_ls_cpu1_bss_start

uint32_t g_ra8_ls_cpu1_bss_start

extern

Referenced by cpu1_reset_handler().

g_ra8_ls_cpu1_data_end

uint32_t g_ra8_ls_cpu1_data_end

extern

Referenced by cpu1_reset_handler().

g_ra8_ls_cpu1_data_load

uint32_t g_ra8_ls_cpu1_data_load

extern

Referenced by cpu1_reset_handler().

g_ra8_ls_cpu1_data_start

uint32_t g_ra8_ls_cpu1_data_start

extern

Referenced by cpu1_reset_handler().

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern

Referenced by main().