cpu1_main.c File Reference

CPU1 (Cortex-M33 secondary core) responder image. More...

#include <stdint.h>
#include "dualcore_mailbox.h"
#include "ra8_err.h"

Include dependency graph for cpu1_main.c:

Go to the source code of this file.

Functions
void	cpu1_reset_handler (void)
	CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.
static void	cpu1_main (void)
	CPU1 application loop: answer the M85's mailbox requests.
static void	cpu1_fault_handler (void)
	CPU1 default fault handler: park the core.

Variables
uint32_t	g_ra8_ls_cpu1_stack_top
	CPU1 stack top (slot 0 of the M33 vector table).
uint32_t	g_ra8_ls_cpu1_data_start
	CPU1 .data run-region start (in SRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_data_end
	CPU1 .data run-region end.
uint32_t	g_ra8_ls_cpu1_data_load
	CPU1 .data load image (in MRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_bss_start
	CPU1 .bss start (in SRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_bss_end
	CPU1 .bss end.
const uintptr_t	g_cpu1_vector_table []

Detailed Description

CPU1 (Cortex-M33 secondary core) responder image.

Tag

[Ring 1 / app] {World: NS}

This is the firmware that runs on the RA8D2's second core, the Cortex-M33. It is compiled as a wholly separate ELF (-mcpu=cortex-m33) and embedded into the M85 ELF as a .cpu1_image blob; the M85 releases this core at runtime via ra8_cpu1_release (HUM Ch 2.9.1 "CPU control registers").

Its job is intentionally tiny so the dual-core plumbing is what stands out:

1. On boot it stamps k_dualcore_m33_signature into the shared mailbox so the M85 can prove the M33 came out of reset.
2. Then it loops: wait for the M85 to bump request_seq, read request, write back request * 3 + 1, bump its liveness counter, and ack by setting reply_seq.

Note

The M33 deliberately does NOT call ra8_log. On hardware each core has its own CoreSight ITM, and the ra8_emulator only echoes the primary core's ITM stream, so an M33 ra8_log line would be invisible in the fake. The M33's proof-of-life is therefore the value it writes into the mailbox (the M85 reads it and logs it on the M33's behalf), which is honest in both the emulator and on silicon.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file cpu1_main.c.

Function Documentation

cpu1_fault_handler()

void cpu1_fault_handler ( void )

static

CPU1 default fault handler: park the core.

Every M33 exception slot routes here. The core stops making forward progress; on hardware a watchdog (if enabled) eventually resets.

Returns

This function never returns.

Note

The core spins in place.

Precondition

A hardware fault or unhandled exception occurred.

Entered via the M33 exception entry path.

Postcondition

The M33 makes no further forward progress.

m33_replies stops advancing, which the M85 can observe.

Note

Shared default for all CPU1 exception vectors.

Since

0.1.0

Definition at line 162 of file cpu1_main.c.

cpu1_main()

void cpu1_main ( void )

static

CPU1 application loop: answer the M85's mailbox requests.

Stamps the boot signature, then services request/reply rounds forever. Each request is transformed by * k_dualcore_m33_mul + k_dualcore_m33_add so a correct reply proves the M33 executed code rather than the M85 reading back its own write. See the file header.

Returns

This function never returns.

Note

Control never leaves the service loop.

Precondition

cpu1_reset_handler has initialised .data/.bss.

The shared mailbox at k_dualcore_mailbox_addr is reachable.

Postcondition

k_dualcore_m33_signature has been written to the mailbox.

The loop never exits.

Note

Single-threaded; runs in M33 thread mode with no RTOS.

Since

0.1.0

Definition at line 72 of file cpu1_main.c.

References dualcore_mailbox(), k_dualcore_m33_add, k_dualcore_m33_mul, k_dualcore_m33_signature, dualcore_mailbox_t::m33_replies, dualcore_mailbox_t::m33_signature, dualcore_mailbox_t::reply, dualcore_mailbox_t::reply_seq, dualcore_mailbox_t::request, and dualcore_mailbox_t::request_seq.

cpu1_reset_handler()

void cpu1_reset_handler

(

void

)

CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.

The M33 boots with uninitialised RAM, so before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. Skipping this leaves file-scope globals holding whatever pattern SRAM held at power-on. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_main, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Definition at line 126 of file cpu1_main.c.

References cpu1_main(), g_ra8_ls_cpu1_bss_end, g_ra8_ls_cpu1_bss_start, g_ra8_ls_cpu1_data_end, g_ra8_ls_cpu1_data_load, and g_ra8_ls_cpu1_data_start.

Variable Documentation

g_cpu1_vector_table

const uintptr_t g_cpu1_vector_table[]

Initial value:

                                     = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
}

Definition at line 183 of file cpu1_main.c.

g_ra8_ls_cpu1_bss_end

uint32_t g_ra8_ls_cpu1_bss_end

extern

CPU1 .bss end.

g_ra8_ls_cpu1_bss_start

uint32_t g_ra8_ls_cpu1_bss_start

extern

CPU1 .bss start (in SRAM_CPU1).

g_ra8_ls_cpu1_data_end

uint32_t g_ra8_ls_cpu1_data_end

extern

CPU1 .data run-region end.

g_ra8_ls_cpu1_data_load

uint32_t g_ra8_ls_cpu1_data_load

extern

CPU1 .data load image (in MRAM_CPU1).

g_ra8_ls_cpu1_data_start

uint32_t g_ra8_ls_cpu1_data_start

extern

CPU1 .data run-region start (in SRAM_CPU1).

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern

CPU1 stack top (slot 0 of the M33 vector table).