cpu1_main.c

Go to the documentation of this file.

 
#include <stdint.h>
 
#include "dualcore_mailbox.h"
#include "ra8_err.h"

extern uint32_t g_ra8_ls_cpu1_stack_top;
extern uint32_t g_ra8_ls_cpu1_data_start;
extern uint32_t g_ra8_ls_cpu1_data_end;
extern uint32_t g_ra8_ls_cpu1_data_load;
extern uint32_t g_ra8_ls_cpu1_bss_start;
extern uint32_t g_ra8_ls_cpu1_bss_end;
 
[[noreturn]] void cpu1_reset_handler(void);

[[noreturn]] static void cpu1_main(void)
{
  volatile dualcore_mailbox_t* mb          = dualcore_mailbox();
  uint32_t                     last_seen   = 0U;
  uint32_t                     reply_count = 0U;
 
  /* Announce we are alive before servicing anything: the M85 polls this
   * field to confirm the M33 left reset and is executing user code. */
  mb->m33_signature = (uint32_t)k_dualcore_m33_signature;
  __asm volatile("dsb" ::: "memory");
 
  while (1) {
    /* Spin until the M85 advances the request sequence. The volatile read
     * forces a fresh load each iteration. Bound: the M85 drives this. */
    while (mb->request_seq == last_seen) {
      __asm volatile("nop");
    }
    last_seen = mb->request_seq;
 
    /* Transform the operand. Reading `request` after observing the seq bump
     * guarantees we see the payload the M85 wrote before bumping the seq. */
    const uint32_t operand = mb->request;
    const uint32_t answer = (operand * (uint32_t)k_dualcore_m33_mul) + (uint32_t)k_dualcore_m33_add;
 
    mb->reply = answer;
    reply_count++;
    mb->m33_replies = reply_count;
    /* Drain the write buffer so the M85 sees `reply` + `m33_replies` before
     * it sees the `reply_seq` ack on the next store. */
    __asm volatile("dsb" ::: "memory");
    mb->reply_seq = last_seen;
  }
}

[[noreturn]] void cpu1_reset_handler(void)
{
  uint32_t* dst = &g_ra8_ls_cpu1_data_start;
  uint32_t* src = &g_ra8_ls_cpu1_data_load;
  while (dst < &g_ra8_ls_cpu1_data_end) {
    *dst = *src;
    dst++;
    src++;
  }
 
  uint32_t* bss = &g_ra8_ls_cpu1_bss_start;
  while (bss < &g_ra8_ls_cpu1_bss_end) {
    *bss = 0U;
    bss++;
  }
 
  cpu1_main();
}

[[noreturn]] static void cpu1_fault_handler(void)
{
  while (1) {
    __asm volatile("nop");
  }
}

#ifndef RA8_OFF_TARGET
/* The vector table is only meaningful in the cross-compiled M33 image. The
 * host unit-test build compile-checks this TU but never links it as an
 * executable, so dropping the table there costs no coverage. */
[[gnu::used, gnu::section(".cpu1_vectors")]] const uintptr_t g_cpu1_vector_table[] = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
};
#endif