cpu1_main.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_err.h"
#include "ra8_ipc.h"
 
extern uint32_t g_ra8_ls_cpu1_stack_top;
extern uint32_t g_ra8_ls_cpu1_data_start;
extern uint32_t g_ra8_ls_cpu1_data_end;
extern uint32_t g_ra8_ls_cpu1_data_load;
extern uint32_t g_ra8_ls_cpu1_bss_start;
extern uint32_t g_ra8_ls_cpu1_bss_end;
 
[[noreturn]] void cpu1_reset_handler(void);
 
typedef enum : uint32_t {
  k_cpu1_pingpong_magic_ping = 0x1234U, 
  k_cpu1_pingpong_magic_pong = 0x4321U, 
} cpu1_main_const_t;
 
typedef enum : uint8_t {
  k_cpu1_pingpong_pair_zero = 0U, 
} cpu1_main_pair_t;
 
/* Self-contained IPC for CPU1 -- avoid the M85 HAL whose accessors
 * the M33 cannot all reach through its NS-controller view. Channel windows
 * via the NS alias (bit 28 set) so the IPCSAR-attributed channels are
 * reachable. HUM Ch 3.2 p 205. */
typedef enum : uintptr_t {
  k_cpu1_ipc_ch0_addr = 0x500200C0UL, 
  k_cpu1_ipc_ch2_addr = 0x50020100UL, 
} cpu1_ipc_addr_t;
 
typedef enum : uint8_t {
  k_cpu1_ipc_off_sta = 0x00U, 
  k_cpu1_ipc_off_txd = 0x08U, 
  k_cpu1_ipc_off_rxd = 0x0CU, 
  k_cpu1_ipc_off_clr = 0x10U, 
} cpu1_ipc_off_t;
 
typedef enum : uint32_t {
  k_cpu1_ipc_sta_rdy = 0x00010000UL, 
  k_cpu1_ipc_clr_all = 0x030100FFUL, 
} cpu1_ipc_mask_t;

typedef enum : uintptr_t {
  k_cpu1_sau_ctrl_addr = 0xE000EDD0UL, 
  k_cpu1_sau_rnr_addr  = 0xE000EDD8UL, 
  k_cpu1_sau_rbar_addr = 0xE000EDDCUL, 
  k_cpu1_sau_rlar_addr = 0xE000EDE0UL, 
} cpu1_sau_reg_t;

typedef enum : uint32_t {
  k_cpu1_sau_periph_ns_base  = 0x50000000UL, 
  k_cpu1_sau_periph_ns_limit = 0x5FFFFFE1UL, 
  k_cpu1_sau_periph_s_base   = 0x40000000UL, 
  k_cpu1_sau_periph_s_limit  = 0x4FFFFFE1UL, 
  k_cpu1_sau_ns_sram_base    = 0x22100000UL, 
  k_cpu1_sau_ns_sram_limit   = 0x221FFFE1UL, 
  k_cpu1_sau_mram_base       = 0x020C0000UL, 
  k_cpu1_sau_mram_limit      = 0x020FFFE1UL, 
} cpu1_sau_region_t;

typedef enum : uintptr_t {
  k_cpu1_probe_reset_addr   = 0x32100200UL, 
  k_cpu1_probe_data_addr    = 0x32100204UL, 
  k_cpu1_probe_bss_addr     = 0x32100208UL, 
  k_cpu1_probe_main_addr    = 0x3210020CUL, 
  k_cpu1_probe_sau_addr     = 0x32100214UL, 
  k_cpu1_probe_iter_addr    = 0x32100220UL, 
  k_cpu1_probe_rxd_addr     = 0x32100224UL, 
  k_cpu1_probe_pong_addr    = 0x32100228UL, 
  k_cpu1_probe_preread_addr = 0x32100230UL, 
  k_cpu1_probe_sta_addr     = 0x32100234UL, 
  k_cpu1_probe_sem_addr     = 0x32100238UL, 
  k_cpu1_probe_reset_s_addr = 0x22190200UL, 
  k_cpu1_ipcsem0_ns_addr    = 0x50020000UL, 
} cpu1_probe_addr_t;

typedef enum : uint32_t {
  k_cpu1_probe_reset_val = 0xC0DEDEADUL, 
  k_cpu1_probe_data_val  = 0xB055A55AUL, 
  k_cpu1_probe_bss_val   = 0xBEEFCAFEUL, 
  k_cpu1_probe_main_val  = 0x11111111UL, 
  k_cpu1_probe_sau_val   = 0x33333333UL, 
  k_cpu1_probe_pre_val   = 0xAAAAAAAAUL, 
} cpu1_probe_val_t;

RA8_INTERNAL static void internal_cpu1_sau_init(void)
{
  /* Region 0: peripherals NS alias (0x50000000-0x5FFFFFE0). */
  *(volatile uint32_t*)k_cpu1_sau_rnr_addr  = 0x00000000UL;                        /* SAU_RNR  */
  *(volatile uint32_t*)k_cpu1_sau_rbar_addr = (uint32_t)k_cpu1_sau_periph_ns_base; /* SAU_RBAR */
  *(volatile uint32_t*)k_cpu1_sau_rlar_addr =
    (uint32_t)k_cpu1_sau_periph_ns_limit; /* SAU_RLAR limit | enable */
  /* Region 1: peripherals S alias (0x40000000-0x4FFFFFE0). */
  *(volatile uint32_t*)k_cpu1_sau_rnr_addr  = 0x00000001UL;
  *(volatile uint32_t*)k_cpu1_sau_rbar_addr = (uint32_t)k_cpu1_sau_periph_s_base;
  *(volatile uint32_t*)k_cpu1_sau_rlar_addr = (uint32_t)k_cpu1_sau_periph_s_limit;
  /* Region 2: NS SRAM range (0x22100000-0x221FFFE0). The CPU1 SRAM bank
   * (0x22190000-0x2219FFE0) now lives inside this window, so one NS region
   * covers both the shared markers and the bank -- a separate bank region
   * would overlap this one, and overlapping SAU regions resolve to Secure,
   * which the permanent-NS M33 cannot reach. */
  *(volatile uint32_t*)k_cpu1_sau_rnr_addr  = 0x00000002UL;
  *(volatile uint32_t*)k_cpu1_sau_rbar_addr = (uint32_t)k_cpu1_sau_ns_sram_base;
  *(volatile uint32_t*)k_cpu1_sau_rlar_addr = (uint32_t)k_cpu1_sau_ns_sram_limit;
  /* Region 3: MRAM_CPU1 code (0x020C0000-0x020FFFE0). */
  *(volatile uint32_t*)k_cpu1_sau_rnr_addr  = 0x00000003UL;
  *(volatile uint32_t*)k_cpu1_sau_rbar_addr = (uint32_t)k_cpu1_sau_mram_base;
  *(volatile uint32_t*)k_cpu1_sau_rlar_addr = (uint32_t)k_cpu1_sau_mram_limit;
  /* Enable SAU (no ALLNS, so unprogrammed defaults to IDAU). */
  *(volatile uint32_t*)k_cpu1_sau_ctrl_addr = 0x00000001UL;
  __asm__ volatile("dsb 0xf" ::: "memory");
  __asm__ volatile("isb 0xf" ::: "memory");
  *(volatile uint32_t*)k_cpu1_probe_sau_addr = (uint32_t)k_cpu1_probe_sau_val; /* SAU configured */
}

[[noreturn]] RA8_INTERNAL static void internal_cpu1_main(void)
{
  *(volatile uint32_t*)k_cpu1_probe_main_addr =
    (uint32_t)k_cpu1_probe_main_val; /* internal_cpu1_main entry */
 
  internal_cpu1_sau_init();
 
  while (1) {
    *(volatile uint32_t*)k_cpu1_probe_iter_addr += 1U; /* loop iter counter */
    *(volatile uint32_t*)k_cpu1_probe_preread_addr =
      (uint32_t)k_cpu1_probe_pre_val; /* pre-IPC-read marker */
    /* TEST: read IPCSEM0 (the simplest IPC reg) first to isolate fault.
     * IPCSEM0 is at 0x40020000 / NS alias 0x50020000.
     * IPCSAR.SAIPCSEM0 (bit 0) was set NS too. */
    const uint32_t sem                         = *(volatile uint32_t*)k_cpu1_ipcsem0_ns_addr;
    *(volatile uint32_t*)k_cpu1_probe_sem_addr = sem; /* IPCSEM0 read survived */
    /* Poll CH2 RX for ping. */
    const uint32_t sta = *(volatile uint32_t*)(k_cpu1_ipc_ch2_addr + k_cpu1_ipc_off_sta);
    *(volatile uint32_t*)k_cpu1_probe_sta_addr = sta; /* STA read survived */
    if ((sta & (uint32_t)k_cpu1_ipc_sta_rdy) == 0U) {
      continue;
    }
    const uint32_t got = *(volatile uint32_t*)(k_cpu1_ipc_ch2_addr + k_cpu1_ipc_off_rxd);
    *(volatile uint32_t*)k_cpu1_probe_rxd_addr = got; /* most recent rxd */
    if (got != (uint32_t)k_cpu1_pingpong_magic_ping) {
      continue;
    }
    /* Push pong onto CH0 TX. */
    *(volatile uint32_t*)(k_cpu1_ipc_ch0_addr + k_cpu1_ipc_off_txd) =
      (uint32_t)k_cpu1_pingpong_magic_pong;
    *(volatile uint32_t*)k_cpu1_probe_pong_addr += 1U; /* pong sent counter */
  }
}

[[noreturn]] void cpu1_reset_handler(void)
{
  /* CPU1 NS-alias-side marker. The M33 here has SECEXT disabled, so it
   * is hardware-locked to the NS controller state; the dedicated SRAM_CPU1
   * bank at 0x22190000 is its physical alias for these BSS reads, but
   * CPU0's J-Link memprobe sees the same bytes through the standard
   * 0x22190000 view. Bench tail: confirm 0xC0DEDEAD before the data
   * copy starts -- it tells us reset_handler actually ran and the
   * MRAM_CPU1 fetch worked. */
  /* Markers placed in NS_SRAM (CPU0 J-Link memprobe can read this view;
   * CPU0's SAU NS_SRAM region 0x22100000-0x221FFFE0 maps NS, and CPU1
   * as a permanent NS controller can write to the same physical bytes
   * through the NS alias 0x32100200). The chip's two views of SRAM
   * see the same backing store. */
  *(volatile uint32_t*)k_cpu1_probe_reset_addr   = (uint32_t)k_cpu1_probe_reset_val;
  *(volatile uint32_t*)k_cpu1_probe_reset_s_addr = (uint32_t)k_cpu1_probe_reset_val;
 
  /* Copy .data from MRAM_CPU1 load address into SRAM_CPU1. The linker
   * defines ``g_ra8_ls_cpu1_data_load`` as LOADADDR(.data) so this
   * works regardless of the absolute MRAM_CPU1 base. */
  uint32_t* dst = &g_ra8_ls_cpu1_data_start;
  uint32_t* src = &g_ra8_ls_cpu1_data_load;
  while (dst < &g_ra8_ls_cpu1_data_end) {
    *dst = *src;
    dst++;
    src++;
  }
  *(volatile uint32_t*)k_cpu1_probe_data_addr =
    (uint32_t)k_cpu1_probe_data_val; /* survived .data copy */
 
  /* Zero .bss in SRAM_CPU1. */
  uint32_t* bss = &g_ra8_ls_cpu1_bss_start;
  while (bss < &g_ra8_ls_cpu1_bss_end) {
    *bss = 0U;
    bss++;
  }
  *(volatile uint32_t*)k_cpu1_probe_bss_addr =
    (uint32_t)k_cpu1_probe_bss_val; /* survived .bss zero */
 
  internal_cpu1_main();
}

[[noreturn]] RA8_INTERNAL static void internal_cpu1_fault_handler(void)
{
  while (1) {
    __asm volatile("nop");
  }
}

#ifndef RA8_OFF_TARGET
/* Vector table only built for the cross-compiled M33 image. The host
 * build does not link this TU as an executable -- it is compile-checked
 * only -- so we can drop the table without losing test coverage. */
[[gnu::used, gnu::section(".cpu1_vectors")]] const uintptr_t g_cpu1_vector_table[] = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
  (uintptr_t)&internal_cpu1_fault_handler,
};
#endif