cpu1_main.c File Reference

CPU1 (Cortex-M33) image: blink LED1 through the HAL PCNTR primitive. More...

#include <stdint.h>
#include "blink_m33_hal.h"
#include "ra8_port_constants.h"

Include dependency graph for cpu1_main.c:

Go to the source code of this file.

Enumerations
enum	m33_blink_const_t : uint32_t { k_blink_spins = 3000000U }
	Blink-loop delay bound. More...

Functions
void	cpu1_reset_handler (void)
	CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.
static void	cpu1_main (void)
	CPU1 application loop: blink LED1 (BLUE, P600) via the HAL primitive.
static void	cpu1_fault_handler (void)
	CPU1 default fault handler: park the core.

Variables
uint32_t	g_ra8_ls_cpu1_stack_top
	CPU1 stack top (slot 0 of the M33 vector table).
uint32_t	g_ra8_ls_cpu1_data_start
	CPU1 .data run-region start (in SRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_data_end
	CPU1 .data run-region end.
uint32_t	g_ra8_ls_cpu1_data_load
	CPU1 .data load image (in MRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_bss_start
	CPU1 .bss start (in SRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_bss_end
	CPU1 .bss end.
const uintptr_t	g_cpu1_vector_table []

Detailed Description

CPU1 (Cortex-M33) image: blink LED1 through the HAL PCNTR primitive.

Tag

[Ring 1 / app] {World: NS}

This is the HAL-based twin of hw_validated/hil/blink_m33/cpu1_main.c. It runs on the RA8D2's secondary Cortex-M33, is compiled as a wholly separate -ffreestanding ELF and embedded into the M85 ELF as a .cpu1_image blob, and the M85 releases it via ra8_cpu1_release (HUM Ch 2.9.1) before sleeping.

The ONE difference from the raw twin is the register access: instead of casting 0x404000C0 to a volatile uint32_t* and hand-rolling the combined {PODR,PDR} PCNTR1 store, it drives board LED1 (BLUE, P600 = PORT6 pin 0) through ra8_pcntr_set_output() – the CPU1-safe, header-only HAL primitive (issue #580). No ra8_hal object is linked; only the freestanding-clean inline accessor is included, so the image stays exactly as freestanding as before. This app exists ALONGSIDE the raw blink_m33 (which is kept as the deliberate raw-MMIO reference), demonstrating that the primitive substitutes at the M33 call site.

Note

The M33 deliberately does NOT call ra8_log: the ra8_emulator echoes only the primary core's ITM, so an M33 log line would be invisible. The proof-of-life is the LED1 transition the M85 never drives.

LED1 powers up routed to PORT, so no PmnPFS / PWPR pin-function setup is needed; the primitive touches only PCNTR1 (direction + output level).

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file cpu1_main.c.

Enumeration Type Documentation

m33_blink_const_t

enum m33_blink_const_t : uint32_t

Blink-loop delay bound.

The pin masks and PCNTR field layout now live inside ra8_pcntr_set_output(); the CPU1 image only owns the visible cadence.

Since

0.1.0

Enumerator
k_blink_spins	Bounded busy-delay spins per LED half-cycle.

Definition at line 62 of file cpu1_main.c.

Function Documentation

cpu1_fault_handler()

void cpu1_fault_handler ( void )

static

CPU1 default fault handler: park the core.

Every M33 exception slot routes here. The core stops making forward progress; on hardware a watchdog (if enabled) eventually resets.

Returns

This function never returns.

Note

The core spins in place.

Precondition

A hardware fault or unhandled exception occurred.

Entered via the M33 exception entry path.

Postcondition

The M33 makes no further forward progress.

The LED stops toggling, which is observable from the M85.

Note

Shared default for all CPU1 exception vectors.

Since

0.1.0

Definition at line 156 of file cpu1_main.c.

cpu1_main()

void cpu1_main ( void )

static

CPU1 application loop: blink LED1 (BLUE, P600) via the HAL primitive.

Each pass calls blink_m33_hal_step() – the shared one-iteration step (blink_m33_hal.h) that toggles the level and drives LED1 to it through ra8_pcntr_set_output() (the register access + HUM citation live in the primitive). A bounded busy-delay paces the blink. The same step is exercised by the host app-level test, so the tested logic is exactly this loop's. The M85 never writes this pin, so the transitions prove the M33 is running. See the file header.

Returns

This function never returns.

Note

Control never leaves the blink loop.

Precondition

cpu1_reset_handler has initialised .data/.bss.

The IOPORT module clock is on (always-on after reset).

Postcondition

PORT6 pin 0 is configured as an output.

The LED1 level alternates on the configured cadence forever.

Note

Single-threaded; runs in M33 thread mode with no RTOS.

Since

0.1.0

Definition at line 88 of file cpu1_main.c.

References blink_m33_hal_step(), k_blink_spins, and k_ra8_level_low.

Referenced by cpu1_reset_handler().

cpu1_reset_handler()

void cpu1_reset_handler

(

void

)

CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.

Copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss before any C code runs; the linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_main, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Definition at line 120 of file cpu1_main.c.

References cpu1_main(), g_ra8_ls_cpu1_bss_end, g_ra8_ls_cpu1_bss_start, g_ra8_ls_cpu1_data_end, g_ra8_ls_cpu1_data_load, and g_ra8_ls_cpu1_data_start.

Variable Documentation

g_cpu1_vector_table

const uintptr_t g_cpu1_vector_table[]

Initial value:

                                     = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
}

Definition at line 177 of file cpu1_main.c.

g_ra8_ls_cpu1_bss_end

uint32_t g_ra8_ls_cpu1_bss_end

extern

CPU1 .bss end.

g_ra8_ls_cpu1_bss_start

uint32_t g_ra8_ls_cpu1_bss_start

extern

CPU1 .bss start (in SRAM_CPU1).

g_ra8_ls_cpu1_data_end

uint32_t g_ra8_ls_cpu1_data_end

extern

CPU1 .data run-region end.

g_ra8_ls_cpu1_data_load

uint32_t g_ra8_ls_cpu1_data_load

extern

CPU1 .data load image (in MRAM_CPU1).

g_ra8_ls_cpu1_data_start

uint32_t g_ra8_ls_cpu1_data_start

extern

CPU1 .data run-region start (in SRAM_CPU1).

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern

CPU1 stack top (slot 0 of the M33 vector table).