Shared-SRAM mailbox layout for the M85 <-> M33 dual-core demo. More...

#include <stdint.h>
#include "ra8_board_ek_ra8d2_dualcore.h"

Include dependency graph for dualcore_mailbox.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	dualcore_mailbox_t
	Cross-core message block backed by a fixed shared-SRAM address. More...

Enumerations
enum	dualcore_mailbox_addr_t : uintptr_t { k_dualcore_mailbox_addr }
	Where this app puts its mailbox inside the board's shared window. More...
enum	dualcore_mailbox_const_t : uint32_t { k_dualcore_m33_signature = 33U , k_dualcore_m33_mul = 3U , k_dualcore_m33_add = 1U , k_dualcore_poll_budget = 20000000UL }
	Compile-time signature and transform constants. More...

Functions
static volatile dualcore_mailbox_t *	dualcore_mailbox (void)
	Typed pointer to the fixed-address shared mailbox.

Detailed Description

Shared-SRAM mailbox layout for the M85 <-> M33 dual-core demo.

Tag: [Ring 6 / APP] {World: S}

This is the contract that lets the two cores of the RA8D2 talk to each other. The Cortex-M85 (primary, "CPU0") and the Cortex-M33 (secondary, "CPU1") do not share a cache, but they DO share the on-chip SRAM. This header pins a small message struct at one fixed SRAM address that both cores agree on, so a write by one core is seen by the other.

Why a fixed address instead of a normal global? Each core is a separate compiled image with its own linker script, so a static global in one image is invisible to the other. A hard-coded shared address is the one name both images can resolve identically. Neither linker script claims the 0x22100000 mailbox word:

the M85 image (linker_script.ld) uses SRAM0+SRAM1, ending at 0x22100000;
the M33 image (linker_script_cpu1.ld) uses a separate 64 KiB block at the top of on-chip SRAM (0x22190000-0x221A0000). So the bytes at 0x22100000 are backed by the same physical SRAM on both sides with no overlap.

Coherency: this app's system_init.c leaves the M85 data cache OFF, so a store from one core is visible to the other once a dsb has drained the write buffer. No cache clean / invalidate dance is needed. The fields are volatile so the compiler emits a real load/store on every access.

Protocol (a request / reply handshake carried by sequence counters):

M85 writes request, issues dsb, then increments request_seq.
M33 spins until request_seq advances. It then reads request, writes reply = request * 3 + 1, increments m33_replies, issues dsb, and sets reply_seq = request_seq.
M85 spins until reply_seq reaches the value it sent, then reads reply and checks it equals request * 3 + 1. The * 3 + 1 is deliberately a tiny computation, not a copy: a correct reply proves the M33 actually executed arithmetic, not merely echoed a byte.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file dualcore_mailbox.h.

Enumeration Type Documentation

◆ dualcore_mailbox_addr_t

enum dualcore_mailbox_addr_t : uintptr_t

Where this app puts its mailbox inside the board's shared window.

The mailbox sits at the base of the CPU0 <-> CPU1 window. The window itself is a board fact, declared once in ra8_board_ek_ra8d2_dualcore.h along with why both linker scripts leave it free; this app only names its own slice of it.

Invariant: k_dualcore_mailbox_addr is 16-byte aligned (cache-line safe).

See also: ra8_board_dualcore_addr_t; dualcore_mailbox_t

Since: 0.1.0

Enumerator
k_dualcore_mailbox_addr	Mailbox base = window base.

Definition at line 72 of file dualcore_mailbox.h.

◆ dualcore_mailbox_const_t

enum dualcore_mailbox_const_t : uint32_t

Compile-time signature and transform constants.

Shared by both core images so the M85 and M33 agree on what a valid reply looks like.

Invariant: k_dualcore_m33_mul and k_dualcore_m33_add define the reply transform both images implement.

See also: dualcore_mailbox_t

Since: 0.1.0

Enumerator
k_dualcore_m33_signature	M33 stamps this once it boots ("33").
k_dualcore_m33_mul	Reply = request * mul + add.
k_dualcore_m33_add	Reply = request * mul + add.
k_dualcore_poll_budget	Bounded spin iters per wait (Rule 2).

Definition at line 89 of file dualcore_mailbox.h.

Function Documentation

◆ dualcore_mailbox()

volatile dualcore_mailbox_t * dualcore_mailbox ( void )

inlinestatic

Typed pointer to the fixed-address shared mailbox.

Inlined so both core images compute the identical address with no shared translation unit. Returns the same physical SRAM location on the M85 and the M33.

Returns: Pointer to the mailbox at k_dualcore_mailbox_addr.

Return values

non-NULL Always; the address is a compile-time constant.

Precondition: The linker scripts of both images leave SRAM2 unallocated.; The M85 data cache is disabled (see file header).

Postcondition: Returns a valid volatile pointer; never NULL.; No side effects.

Note: Callable from either core; the pointer arithmetic is identical.

Since: 0.1.0

Definition at line 150 of file dualcore_mailbox.h.

References k_dualcore_mailbox_addr.

Referenced by cpu1_main(), and main().

Data Structures