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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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Shared-SRAM message layout for the CPU0 <-> CPU1 ping-pong demo. More...
Go to the source code of this file.
Data Structures | |
| struct | cpu1_pingpong_shared_t |
| Cross-CPU message struct backed by a fixed SRAM address. More... | |
Enumerations | |
| enum | cpu1_pingpong_addr_t : uintptr_t { k_cpu1_pingpong_shared_addr } |
| Where this app puts its shared block inside the board's window. More... | |
| enum | cpu1_pingpong_shared_const_t : uint32_t { k_cpu1_pingpong_magic_ping = 0x1234U , k_cpu1_pingpong_magic_pong = 0x4321U , k_cpu1_pingpong_poll_budget = 2000000UL } |
| Compile-time magics + spin budget for the shared block. More... | |
Functions | |
| static volatile cpu1_pingpong_shared_t * | internal_shared (void) |
| Typed pointer to the fixed-address shared message block. | |
Shared-SRAM message layout for the CPU0 <-> CPU1 ping-pong demo.
The CPU0 (M85) <-> CPU1 (M33) ping-pong cannot use the IPC channels' TXD/RXD registers because the chip's IPC security-attribution (SAIPCIRn) is mutually exclusive S xor NS, and CPU1 has SECEXT disabled (HUM Ch 2) so it can only execute non-secure. With CPU0 also booting non-secure in this app's build, neither core can write IPCSAR to flip the channel to NS, and the default secure-only channel blocks both ends.
This file pins a small message struct at the start of the upper on-chip SRAM region (0x22100000), just above CPU0's allocated SRAM (which ends at 0x22100000) and below CPU1's dedicated 64 KiB bank at the top of SRAM (0x22190000-0x221A0000). Both CPUs' linker scripts leave 0x22100000 unclaimed, so the same physical bytes back the same struct on both sides.
Protocol: monotonic sequence counters carry the wakeup signal; the payload words carry the data.
No IPC peripheral is touched.
The D-cache is disabled in this app's system_init.c (see the internal_enable_dcache call site – it's referenced as (void)internal_enable_dcache; so the function isn't actually invoked), so no cache-clean / invalidate dance is needed across the two CPUs.
Definition in file shared_pingpong.h.
| enum cpu1_pingpong_addr_t : uintptr_t |
Where this app puts its shared block inside the board's window.
The block sits at the base of the CPU0 <-> CPU1 window. The window itself is a board fact, declared once in ra8_board_ek_ra8d2_dualcore.h along with why both linker scripts leave it free; this app only names its own slice of it.
| Enumerator | |
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| k_cpu1_pingpong_shared_addr | Shared block = window base. |
Definition at line 70 of file shared_pingpong.h.
| enum cpu1_pingpong_shared_const_t : uint32_t |
Compile-time magics + spin budget for the shared block.
Both images agree on these so a stale or garbage read on either side surfaces as a payload mismatch rather than as a hang.
| Enumerator | |
|---|---|
| k_cpu1_pingpong_magic_ping | CPU0 ping payload. |
| k_cpu1_pingpong_magic_pong | CPU1 pong payload. |
| k_cpu1_pingpong_poll_budget | Max spin iters per direction. |
Definition at line 85 of file shared_pingpong.h.
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inlinestatic |
Typed pointer to the fixed-address shared message block.
Inlined so both CPUs land on identical addressing without needing a separate translation unit.
Definition at line 129 of file shared_pingpong.h.
References k_cpu1_pingpong_shared_addr, and RA8_INTERNAL.