90typedef enum : uint32_t {
148 __asm
volatile(
"dsb" :::
"memory");
156 __asm
volatile(
"nop");
161 uint32_t next_seq = 1U;
168 __asm
volatile(
"dsb" :::
"memory");
void main(void)
Secure fallback main entry point.
static volatile cache_coherency_shared_t * internal_shared(void)
Typed pointer to the fixed-address shared message block.
uint32_t g_ra8_ls_cpu1_mram_start
static RA8_INTERNAL bool internal_wait_for_pong(const volatile cache_coherency_shared_t *shared, uint32_t target)
Poll until pong_seq reaches target or the budget runs out.
volatile uint32_t g_cpu1_pingpong_release_err
Captured ra8_cpu1_release return code.
volatile uint32_t g_cpu1_pingpong_step
Boot progress tracker.
volatile uint32_t g_cpu1_pingpong_match
HIL liveness counter – incremented on every successful CPU0 -> CPU1 -> CPU0 ping/pong round-trip (got...
volatile uint32_t g_cpu1_pingpong_mismatch
HIL failure counter – incremented whenever a round-trip cannot complete: TX failed,...
cpu1_pingpong_err_sentinel_t
Sentinel for g_cpu1_pingpong_release_err ("none yet").
@ k_cpu1_pingpong_err_none
Cpu1 pingpong error none.
@ k_cpu1_pingpong_magic_ping
Cpu1 pingpong magic ping.
@ k_cpu1_pingpong_magic_pong
Cpu1 pingpong magic pong.
uint32_t g_ra8_ls_cpu1_stack_top
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Boot entry points shared between a vector table and its startup code.
Dual-core (CPU0 / CPU1) lifecycle helper – public API.
ra8_err_t ra8_cpu1_release(void *entry, void *sp)
Release CPU1 (Cortex-M33) from reset and start it executing.
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Shared-SRAM message layout for the CPU0 <-> CPU1 ping-pong demo.
@ k_cpu1_pingpong_poll_budget
Max spin iters per direction.
Cross-CPU message struct backed by a fixed SRAM address.
volatile uint32_t ping_seq
CPU0 increments after writing payload.
volatile uint32_t pong_seq
CPU1 sets to match ping_seq after reply.
volatile uint32_t ping_payload
CPU0 writes, CPU1 reads.
volatile uint32_t pong_payload
CPU1 writes, CPU0 reads.