ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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main.c
Go to the documentation of this file.
1
24
25#include <stdint.h>
26
27#include "ra8_boot_entry.h"
28#include "ra8_dual_core.h"
29#include "ra8_err.h"
30#include "shared_pingpong.h"
31
32extern uint32_t g_ra8_ls_cpu1_mram_start;
33extern uint32_t g_ra8_ls_cpu1_stack_top;
34
51volatile uint32_t g_cpu1_pingpong_match = 0U;
52
69volatile uint32_t g_cpu1_pingpong_mismatch = 0U;
70
80volatile uint32_t g_cpu1_pingpong_step = 0U;
81
90typedef enum : uint32_t {
93
95
118 uint32_t target)
119{
120 for (uint32_t i = 0U; i < (uint32_t)k_cpu1_pingpong_poll_budget; ++i) {
121 if (shared->pong_seq == target) {
122 return true;
123 }
124 }
125 return false;
126}
127
138void main(void)
139{
140 volatile cpu1_pingpong_shared_t* shared = internal_shared();
141 /* CPU0 owns initialization of the shared block. Zero everything
142 * before releasing CPU1 so CPU1 can rely on starting from a known
143 * clean state. */
144 shared->ping_seq = 0U;
145 shared->pong_seq = 0U;
146 shared->ping_payload = 0U;
147 shared->pong_payload = 0U;
148 __asm volatile("dsb" ::: "memory");
149
152 g_cpu1_pingpong_release_err = (uint32_t)err;
154 if (err != k_ra8_ok) {
155 while (1) {
156 __asm volatile("nop");
157 }
158 }
159
161 uint32_t next_seq = 1U;
162
163 while (1) {
165 /* Write payload before bumping ping_seq so CPU1 always observes
166 * the new payload on the same iteration the sequence advances. */
167 shared->ping_payload = (uint32_t)k_cpu1_pingpong_magic_ping;
168 __asm volatile("dsb" ::: "memory");
169 shared->ping_seq = next_seq;
170
171 if (!internal_wait_for_pong(shared, next_seq)) {
173 next_seq += 1U;
174 continue;
175 }
176 if (shared->pong_payload != (uint32_t)k_cpu1_pingpong_magic_pong) {
178 next_seq += 1U;
179 continue;
180 }
182 next_seq += 1U;
183 }
184}
void main(void)
Secure fallback main entry point.
Definition main.c:37
static volatile cache_coherency_shared_t * internal_shared(void)
Typed pointer to the fixed-address shared message block.
uint32_t g_ra8_ls_cpu1_mram_start
static RA8_INTERNAL bool internal_wait_for_pong(const volatile cache_coherency_shared_t *shared, uint32_t target)
Poll until pong_seq reaches target or the budget runs out.
Definition main.c:231
volatile uint32_t g_cpu1_pingpong_release_err
Captured ra8_cpu1_release return code.
Definition main.c:94
volatile uint32_t g_cpu1_pingpong_step
Boot progress tracker.
Definition main.c:80
volatile uint32_t g_cpu1_pingpong_match
HIL liveness counter – incremented on every successful CPU0 -> CPU1 -> CPU0 ping/pong round-trip (got...
Definition main.c:51
volatile uint32_t g_cpu1_pingpong_mismatch
HIL failure counter – incremented whenever a round-trip cannot complete: TX failed,...
Definition main.c:69
cpu1_pingpong_err_sentinel_t
Sentinel for g_cpu1_pingpong_release_err ("none yet").
Definition main.c:90
@ k_cpu1_pingpong_err_none
Cpu1 pingpong error none.
Definition main.c:91
@ k_cpu1_pingpong_magic_ping
Cpu1 pingpong magic ping.
Definition cpu1_main.c:32
@ k_cpu1_pingpong_magic_pong
Cpu1 pingpong magic pong.
Definition cpu1_main.c:33
uint32_t g_ra8_ls_cpu1_stack_top
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Boot entry points shared between a vector table and its startup code.
Dual-core (CPU0 / CPU1) lifecycle helper – public API.
ra8_err_t ra8_cpu1_release(void *entry, void *sp)
Release CPU1 (Cortex-M33) from reset and start it executing.
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
Shared-SRAM message layout for the CPU0 <-> CPU1 ping-pong demo.
@ k_cpu1_pingpong_poll_budget
Max spin iters per direction.
Cross-CPU message struct backed by a fixed SRAM address.
volatile uint32_t ping_seq
CPU0 increments after writing payload.
volatile uint32_t pong_seq
CPU1 sets to match ping_seq after reply.
volatile uint32_t ping_payload
CPU0 writes, CPU1 reads.
volatile uint32_t pong_payload
CPU1 writes, CPU0 reads.