ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
Loading...
Searching...
No Matches
main.c File Reference

SRAM ECC bring-up + error-status monitor demo (EK-RA8D2). More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_isr.h"
#include "ra8_mstp.h"
#include "ra8_sram.h"
#include "ra8_time.h"
Include dependency graph for main.c:

Go to the source code of this file.

Enumerations

enum  ecc_demo_config_t : uint32_t {
  k_ecc_demo_baud = 115200U ,
  k_ecc_demo_period_ms = 1000U ,
  k_ecc_demo_pat_xor = 0x5A5A5A5AU
}
 Compile-time settings. More...
enum  ecc_demo_geom_t : uint8_t {
  k_ecc_demo_bank = 2U ,
  k_ecc_demo_test_words = 64U
}
 ECC target geometry. More...

Functions

static void internal_panic_halt (void)
 Park forever after a fatal ECC demo initialization failure.
static uint32_t internal_pattern (uint32_t i)
 Calculate the deterministic read/write test pattern for one word.
static void internal_setup_or_halt (void)
 Bring CGC, SysTick, SCI8, LEDs, and MSTP up.
static ra8_err_t internal_configure (void)
 Enable full ECC + zero-init on spare bank 2 and resolve its base.
static ra8_err_t internal_sample (uint8_t *out_ok)
 Round-trip a pattern through the ECC-protected buffer, then read the ECC status, and fold both into the verdict.
void main (void)
 The application entry point Reset_Handler hands control to.

Variables

static const char * s_tag = "ecc_demo"
 Diagnostic / log tag.
static const uint8_t s_ecc_demo_ok_msg [] = "ecc: sram2 ecc=on rw=ok ok=Y\r\n"
 Output line tags.
static const uint8_t s_ecc_demo_bad_msg [] = "ecc: sram2 rw=BAD ok=N\r\n"
volatile uint32_t g_ecc_ok = 0U
 1 when ECC is healthy: rw round-trips and no error is latched.
volatile uint32_t g_ecc_rw_ok = 0U
 1 when the ECC-protected buffer read back exactly.
volatile uint32_t g_ecc_esr = 0U
 Last raw SRAMESR snapshot (0 = no ECC error latched).
volatile uint32_t g_ecc_1bit = 0U
 Per-bank 1-bit-error bitmap from the last SRAMESR read (bit n = bank n).
volatile uint32_t g_ecc_2bit = 0U
 Per-bank 2-bit-error bitmap from the last SRAMESR read (bit n = bank n).
volatile uint32_t g_ecc_heartbeat = 0U
 Bumps once per main-loop pass – liveness for headless probes.
static volatile uint32_t * s_ecc_buf = nullptr
 Base of the ECC-protected bank, resolved at init.

Detailed Description

SRAM ECC bring-up + error-status monitor demo (EK-RA8D2).

Tag
[Ring 6 / APP] {World: S}

The RA8D2 SRAM controller can attach SECDED ECC to each 512 KiB bank: 1-bit errors are corrected (and optionally latched), 2-bit errors are uncorrectable and raise an NMI (or reset). This demo enables full ECC ("with-check") on a spare SRAM bank, proves an ECC-protected read/write round-trips, and polls the ECC status register (SRAMESR) – the hardware-error-reporting path – reporting it once a second.

Why bank 2 (0x2210_0000). ECC with-check requires the bank's ECC codes to be initialised first (zero_init), otherwise reading never-written words raises a spurious 2-bit error -> NMI. The zero_init pass rewrites the whole bank, so it must target memory the program does not use. This app's linker places .data / .bss / stack in the first 1 MiB (banks 0-1, 0x2200_0000..0x2210_0000); banks 2-3 are unused, so ECC + zero-init on bank 2 is safe. on_error stays NMI but no error is injected, so the NMI never fires in this demo.

Bring-up: CGC + SysTick + SCI8 + LEDs + MSTP. Once a second: "ecc: sram2 ecc=on rw=ok ok=Y\r\n" (the latched 1-bit / 2-bit error masks go to g_ecc_1bit / g_ecc_2bit for on-silicon probing). LED1 toggles while ECC is healthy; LED2 toggles on a fault.

Bare EK-RA8D2 only – no shields or external transceivers.

Note
Headless-emulator status. tools/ra8_emulator shadows the SRAM ECC control window (SRAMCRn / SRAMESR) so the bring-up + status read run and report ok=Y with a clean ESR – but a real ECC error only appears when a bit actually flips, which needs silicon (or an error-injection register). The detection half therefore lives in hw_pending/. See README.md for the bench plan.
Copyright
Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT
Since
0.1.0

Definition in file main.c.

Enumeration Type Documentation

◆ ecc_demo_config_t

enum ecc_demo_config_t : uint32_t

Compile-time settings.

Enumerator
k_ecc_demo_baud 

SCI8 baud rate.

k_ecc_demo_period_ms 

Delay between status reads.

k_ecc_demo_pat_xor 

Per-word rw-test pattern XOR.

Definition at line 62 of file main.c.

◆ ecc_demo_geom_t

enum ecc_demo_geom_t : uint8_t

ECC target geometry.

Enumerator
k_ecc_demo_bank 

Spare SRAM bank 2 (program uses 0-1).

k_ecc_demo_test_words 

rw round-trip words (256 B).

Definition at line 69 of file main.c.

Function Documentation

◆ internal_configure()

ra8_err_t internal_configure ( void )
staticnodiscard

Enable full ECC + zero-init on spare bank 2 and resolve its base.

Banks 0/1/3 stay ECC-disabled (just clock-ungated). Bank 2 gets with-check ECC, 1-bit latch, a 128 KiB ECC region, and the zero-init pass that lays down valid ECC across the bank so no spurious 2-bit error fires. on_error is NMI, but this demo injects no error.

MC/DC:
Sequential init guards (no compound decision); 2 vectors – init OK / init rejects (host-tested).
Returns
ra8_err_t from ra8_sram_init / ra8_sram_get_bank_info.
Return values
k_ra8_okBank 2 was initialized and its base was published.
(other)The first SRAM initialization or bank-info error.
Precondition
CGC + MSTP up; IRQs masked or single-threaded init.
No other context is configuring the SRAM controller.
Postcondition
s_ecc_buf points at bank 2's ECC-protected base.
On failure, the HAL error is returned unchanged.
Note
Not thread-safe; it mutates global SRAM controller state.
Since
0.1.0

Definition at line 226 of file main.c.

References ra8_sram_config_t::banks, ra8_sram_bank_info_t::data_base, ra8_sram_bank_cfg_t::ecc_mode, ra8_sram_bank_cfg_t::eccrgn, ra8_sram_bank_cfg_t::enable_1bit_latch, k_ecc_demo_bank, k_ra8_ok, k_ra8_sram_ecc_with_chk, k_ra8_sram_on_error_interrupt, k_ra8_sram_region_128kb, ra8_sram_bank_cfg_t::on_error, RA8_INTERNAL, ra8_sram_get_bank_info(), ra8_sram_init(), s_ecc_buf, and ra8_sram_bank_cfg_t::zero_init.

◆ internal_panic_halt()

void internal_panic_halt ( void )
static

Park forever after a fatal ECC demo initialization failure.

Repeatedly executes WFI while preserving SRAM status for debug.

Precondition
Called only from boot failure or the terminal foreground path.
The caller does not require recovery without reset.
Postcondition
The core stays in WFI until external intervention.
No further ECC-protected SRAM access is requested.
Note
Not thread-safe; this is a terminal single-threaded path.
Since
0.1.0

Definition at line 139 of file main.c.

References RA8_INTERNAL.

◆ internal_pattern()

uint32_t internal_pattern ( uint32_t i)
static

Calculate the deterministic read/write test pattern for one word.

Squares the index with defined unsigned wraparound and XORs the fixed salt so neighboring test words differ.

Parameters
[in]iZero-based word index.
Returns
Pattern to write at that index.
Return values
0..UINT32_MAXDeterministic wrapped arithmetic result.
Precondition
i is a valid test-buffer index.
The compile-time pattern salt is fixed for the test run.
Postcondition
No hardware or application state is modified.
Repeated calls with the same index return the same value.
Note
Pure and reentrant.
Since
0.1.0

Definition at line 160 of file main.c.

References k_ecc_demo_pat_xor, and RA8_INTERNAL.

Referenced by internal_sample().

◆ internal_sample()

ra8_err_t internal_sample ( uint8_t * out_ok)
staticnodiscard

Round-trip a pattern through the ECC-protected buffer, then read the ECC status, and fold both into the verdict.

Parameters
[out]out_ok1 when the buffer read back exactly AND no 1-bit or 2-bit ECC error is latched.
MC/DC:
Decision ok = rw_ok (the ECC-protected round-trip; single condition) – 2 vectors, match (steady state) + mismatch (host-tested). The latched 1-bit / 2-bit error masks are reported via globals, not gated, since ra8_emulator does not model ECC.
Returns
ra8_err_t from ra8_sram_get_status.
Return values
k_ra8_err_null_ptrout_ok was NULL.
Precondition
internal_configure succeeded (s_ecc_buf valid).
out_ok points to writable caller-owned storage.
Postcondition
g_ecc_rw_ok / g_ecc_esr updated.
On success, all exported ECC status snapshots match the sampled bank.
Note
Not thread-safe; it writes the shared ECC buffer and exported state.
Since
0.1.0

Definition at line 270 of file main.c.

References g_ecc_1bit, g_ecc_2bit, g_ecc_esr, g_ecc_rw_ok, internal_pattern(), k_ecc_demo_test_words, k_ra8_err_not_initialized, k_ra8_ok, ra8_sram_status_t::one_bit_mask, RA8_CHECK_NULL_PTR, RA8_INTERNAL, ra8_sram_get_status(), ra8_sram_status_t::raw_esr, s_ecc_buf, s_tag, and ra8_sram_status_t::two_bit_mask.

◆ internal_setup_or_halt()

void internal_setup_or_halt ( void )
static

Bring CGC, SysTick, SCI8, LEDs, and MSTP up.

Initializes foreground-loop dependencies in order and parks on the first failed HAL operation.

Precondition
Reset startup initialized static storage and the vector table.
Called once before global interrupt enable.
Postcondition
On return, delays, console output, module clocks, and LEDs are ready.
The ECC test bank remains unconfigured until internal_configure.
Note
Not thread-safe; it owns global peripheral initialization.
Since
0.1.0

Definition at line 176 of file main.c.

References internal_panic_halt(), k_ecc_demo_baud, k_ra8_board_led1, k_ra8_board_led2, k_ra8_clock_id_cpuclk0, k_ra8_ok, ra8_board_led_init(), ra8_board_uart_console_init(), ra8_cgc_get_clock_hz(), ra8_cgc_init(), RA8_INTERNAL, ra8_mstp_init(), and ra8_time_init().

◆ main()

void main ( void )

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has configured the clock tree and VTOR.
Postcondition
Control does not return; the image runs until reset or halt.
Any value the application wanted to report has been logged, not returned.
Note
Not thread-safe; single-threaded startup context only.
Warning
Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.
See also
SystemInit()
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the CPU stays in the playback loop forever.
On any HAL init failure the function halts in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the CPU stays in the sweep loop forever.
On any HAL init failure the function halts in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition
Reset_Handler has copied .data and zeroed .bss.
Postcondition
On clean entry the kernel runs the worker thread once.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the kernel runs the worker thread forever.
On any HAL init failure the function halts in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition
Reset_Handler has copied .data + zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
CPUCLK0 is raised to the PLL1 target before the kernel starts.
On clean entry the SD card thread runs forever.
On any HAL init failure the function halts in __WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the CPU stays in the iso-IN feed loop forever.
On any HAL init failure the function halts in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition
Boot init has completed.
The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).
Postcondition
Diagnostic counter latched, CPU parked in a halt loop.
Function never returns.
Note
Single-threaded entry.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.
On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.
On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.
Postcondition
The shelf scans on the panel; taps open books, browse, and read.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The slab/arena/tile/vmem banner is emitted; the CPU then loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
On success the cache globals are latched and g_pc_heartbeat advances.
On any failure g_pc_err is non-zero and the CPU parks (no heartbeat).
Since
0.1.0

The application entry point Reset_Handler hands control to.

Profiles power modes once a second.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the CPU stays in the profile + blink loop.
On any HAL hard error LED2 latches ON.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
The shared board boot files installed the vector table.
Postcondition
The demo has run once and its verdict banner is streaming steadily.
The CPU idles re-emitting the banner (or halts after a fatal init error).
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, SPI, and SD card, then runs the shared ra8_io VFS round-trip over the SD-over-SPI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On a clean run the CPU loops forever after the PASS banner.
On any failure the function prints FAIL and halts in WFI.
Note
Not thread-safe; this is the single-threaded app entry.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging and the console, brings up the OSPI NOR volume, runs the erase-before-write round-trip, and prints a single PASS/FAIL verdict line over SCI8 before parking in an infinite loop.

Precondition
SystemInit configured VTOR / FPU / priority grouping.
The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).
Postcondition
Exactly one PASS or FAIL verdict line has been queued on SCI8.
Control parks in an infinite loop; the function never returns.
Note
Single-threaded; runs to the park loop on the main stack.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The page-count + render-hash banner is emitted; the CPU loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The cal=OK / cal=SKIP result and the finger-free touchcal: ready sentinel are emitted; the CPU then loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The open=OK touch banner is emitted; the CPU then loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Both USB controllers' clocks and pins come up before the kernel so the workers only deal with stack bring-up.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR, FPU, priority grouping.
Postcondition
On clean entry the CPU stays in tx_kernel_enter forever.
On any HAL init failure the function halts in WFI.
Note
Single entry point; not re-entrant.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging and the clock tree, releases the Cortex-M33 (which then blinks LED1 via ra8_pcntr_set_output()), and idles. See the file header.

Precondition
SystemInit has completed core bring-up.
The M33 is held in reset by hardware until released here.
Postcondition
The M33 has been released and is blinking LED1.
This function never returns to its caller.
Note
Single-threaded; no RTOS on the M85 in this template.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
The application links ra8_c6link and ESP-hosted generated codecs.
No hardware validation is inferred from this function.
Postcondition
No c6link operation is attempted.
No network or storage state is modified.
Note
Single-threaded compile fixture.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the cacheable-SRAM round-trip with the D-cache that SystemInit() enabled through ra8_cache_dcache_enable(), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU + RA8_BOOT_CACHE_VIA_HAL).

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit enabled the MPU + I-cache + D-cache via the ra8_cache HAL.
Postcondition
Exactly one banner (PASS or FAIL) has been emitted.
The core is parked in WFI.
Note
Single-threaded; no RTOS and no IRQ sources in this template.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, releases the Cortex-M33 into the emitter, yields until it signals done, validates the blob the M33 built, then logs the PASS/FAIL verdict and the chapter count read back from the blob. See the file header for the offload narrative.

Precondition
SystemInit has completed core bring-up.
The M33 is held inactive by hardware until released here.
Postcondition
The M33 has built a RABOOK1 blob and the M85 has validated it.
This function never returns to its caller.
Note
Single-threaded; no RTOS on the M85 in this example.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
On success the CPU heartbeats after epaper: PASS.
On any HAL error the console prints epaper: FAIL and the red LED latches on.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The chapters/toc/cover banner is emitted; CPU loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The reader loop runs forever, redrawing on each tap.
A page-1 banner is emitted once after the first render.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The cover-size / framebuffer-CRC banner is emitted; CPU loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The panel shows the reader screen and the input loop runs forever.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, arms the IPC0 wake and configures the LPM block, releases the Cortex-M33 into the reader, waits for the first held page, logs the page-0 verdict, then runs the #150 mode-switch cycle – parking in low-power WFI and waking on the M33's page-turn pokes – before logging the handoff verdict and parking for good. See the file header for the narrative.

Precondition
SystemInit has completed core bring-up.
The M33 is held inactive by hardware until released here.
Postcondition
The M33 has rendered + re-rendered the held page and the M85 is parked.
This function never returns to its caller.
Note
Single-threaded; no RTOS on the M85 in this example.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The boot banner is emitted; the reader loop services taps forever.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up the timebase then measures forever.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the CPU stays in the measure + blink loop forever.
On any HAL init failure the function halts in WFI.
Note
Never returns.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Arms the RIIC1 target and polls the dispatcher.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
The CPU stays in the dispatch poll loop forever.
On any fatal init error the CPU parks in riic_target_panic_halt.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On a clean run the PASS banner is printed and the CPU loops in WFI.
On any failure the function prints a FAIL line and halts.
Note
Not thread-safe; single-threaded app entry.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the CPU stays in the read + print loop forever.
On any HAL hard error LED2 latches ON and the loop exits.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up the LIN commander then drives frames.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the CPU stays in the LIN-frame + blink loop forever.
On any HAL init failure the function halts in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, "renders" page 0 into the shared mailbox, releases the Cortex-M33 into its hold loop, and parks the M85 in low-power WFI sleep. See the file header for the power-saving narrative.

Precondition
SystemInit has completed core bring-up.
The M33 is held inactive by hardware until released here.
Postcondition
The M33 owns the held page and the M85 is parked.
This function never returns to its caller.
Note
Single-threaded; no RTOS on the M85 in this example.
Since
0.1.0

The application entry point Reset_Handler hands control to.

The USB clock, pins, console, and the SD card all come up before the kernel so the worker only deals with USB stack bring-up.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR, FPU, priority grouping.
Postcondition
On clean entry the CPU stays in tx_kernel_enter forever.
On any HAL init failure the function halts in WFI.
Note
Single entry point; not re-entrant.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit configured VTOR / FPU.
Postcondition
On clean bring-up the CPU stays in the poll loop.
On any HAL init failure the function halts in WFI.
Note
Single entry point; not re-entrant.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler initialized static storage.
SystemInit configured VTOR, FPU, and priority grouping.
Postcondition
The startup banner is printed once.
Control enters ThreadX and never returns normally.
Note
The #707 freestanding contract is declared by ra8_boot_entry.h.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On a clean run the PASS banner is printed and the CPU heartbeats forever.
On any failure LED2 latches ON and the CPU parks.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the three-step self-test (MPU enabled, canonical boot map, Device MMIO), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit installed the boot map via ra8_mpu_apply_boot_map().
Postcondition
Exactly one banner (PASS or a step-specific FAIL) has been emitted.
The core is parked in WFI.
Note
Single-threaded; no RTOS and no IRQ sources in this template.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler initialised the C runtime; SystemInit ran.
The EK-RA8D2 J-Link OB VCOM console is attached for the banner.
Postcondition
The commit + rollback attempts have executed against extra-MRAM.
The verdict banner is emitted once per report cycle.
Note
Single entry point; not re-entrant.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging + console, brings up the MRAM volume, runs the wear-levelling + power-cycle-survival flow, and prints a single PASS/FAIL verdict.

Precondition
SystemInit configured VTOR / FPU / priority grouping.
The extra-MRAM region is present (modelled in ra8_emulator, real on silicon).
Postcondition
Exactly one PASS or FAIL verdict line has been queued on SCI8.
Control parks in an infinite loop; the function never returns.
Note
Single-threaded; runs to the park loop on the main stack.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging + console, brings up the MRAM volume, runs the program/erase round-trip, and prints a single PASS/FAIL verdict.

Precondition
SystemInit configured VTOR / FPU / priority grouping.
The extra-MRAM region is present (modelled in ra8_emulator, real on silicon).
Postcondition
Exactly one PASS or FAIL verdict line has been queued on SCI8.
Control parks in an infinite loop; the function never returns.
Note
Single-threaded; runs to the park loop on the main stack.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, and SDHI bus pins, runs the native SD card identification, fills the payload, then runs the full ra8_io VFS round-trip over the native-SDHI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On a clean run the CPU loops forever after the PASS banner.
On any failure the function prints FAIL and halts in WFI.
Note
Not thread-safe; this is the single-threaded app entry.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up the console and both stdio sinks, retargets the engine's stdio to the in-RAM capture sink, runs the two-backend swap, replays the RAM capture out of the UART, and prints a single PASS/FAIL verdict per abstraction before parking in an infinite loop.

Precondition
SystemInit configured VTOR / FPU / priority grouping.
The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).
Postcondition
A PASS or FAIL verdict line has been queued on SCI8 for each abstraction.
Control parks in an infinite loop; the function never returns.
Note
Single-threaded; runs to the park loop on the main stack.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, and SDHI bus pins, runs the native SD card identification, fills the payload, then writes + reads + compares one raw 512-byte block straight against ra8_sdcard. On success it prints the exact PASS banner; on any failure it prints FAIL and parks the core.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On a clean run the CPU loops forever after the PASS banner.
On any failure the function prints FAIL and halts in WFI.
Note
Not thread-safe; this is the single-threaded app entry.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The whoami PASS banner is emitted; the CPU then loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII + RSIP, then ThreadX.

Precondition
Reset_Handler has copied .data and zeroed .bss.
Postcondition
On clean entry the kernel runs the worker thread once.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, the FPU and the priority grouping.
Postcondition
The banner was printed exactly once.
Control passed to ThreadX and never came back.
Note
Everything after tx_kernel_enter happens on ThreadX; the panic-halt below is reached only if the kernel refuses to start.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, the FPU and the priority grouping.
Postcondition
The banner and the resolved pin map were printed exactly once.
Control passed to ThreadX and never came back.
Note
Everything after tx_kernel_enter happens on ThreadX; the panic-halt below is reached only if the kernel refuses to start.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, the FPU and priority grouping.
Postcondition
The probe ran exactly once and printed its verdict.
The CPU stays in a slow heartbeat loop afterwards.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, the FPU and the priority grouping.
Postcondition
The banner was printed exactly once.
Control passed to ThreadX and never came back.
Note
Everything after tx_kernel_enter runs on ThreadX; the panic-halt below is reached only if the kernel refuses to start.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Initializes and arms ADC_B, formats each successful channel sample without variadic I/O, emits the verdict, toggles LED1, and delays.

Precondition
Reset startup and SystemInit completed successfully.
The selected ADC channel matches the board analog connection.
Postcondition
Every PASS verdict follows a successful channel read.
Any read or LED failure leads to the terminal panic helper.
Note
Does not return during normal operation.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
On success the PASS banner is emitted; otherwise a FAIL line is.
The CPU parks in WFI (observable on ra8_emulator until its budget).
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, releases the Cortex-M33 (which then blinks LED1), and idles. See the file header for the teaching narrative.

Precondition
SystemInit has completed core bring-up.
The M33 is held in reset by hardware until released here.
Postcondition
The M33 has been released and is blinking LED1.
This function never returns to its caller.
Note
Single-threaded; no RTOS on the M85 in this template.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR / FPU / priority grouping.
Postcondition
The IDCODE/checks PASS banner is emitted; the CPU then loops in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

See the file header for the full behaviour summary.

Precondition
SystemInit has enabled the caches + MPU (this build defines RA8_BOOT_ENABLE_CACHE_MPU).
The M33 is held in reset by hardware until released here.
Postcondition
The M33 has been released and the round-trip loop is running.
This function never returns to its caller.
Note
Single-threaded; no RTOS on the M85 in this template.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the three-step self-test (cacheable SRAM, RO MRAM const, Device MMIO), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches and MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU).

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit enabled the MPU + I-cache + D-cache (cache+MPU build).
Postcondition
Exactly one banner (PASS or a step-specific FAIL) has been emitted.
The core is parked in WFI.
Note
Single-threaded; no RTOS and no IRQ sources in this template.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR, FPU and priority grouping.
Postcondition
The verdict banner is on SCI8 and the CPU parks.
The result globals hold the outcome for SWD probing.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Lights HOCO + PLL, then runs a 1 Hz blink.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit has set VTOR, FPU, and priority grouping.
Postcondition
On clean entry the CPU stays in the toggle loop forever.
On any HAL init failure the function halts in WFI.
Since
0.1.0

The application entry point Reset_Handler hands control to.

See file header for behaviour summary.

Precondition
Boot init has completed.
CPU1 is held in reset.
Postcondition
CPU1 released and the ping-pong loop running.
Function never returns.
Note
Single-threaded entry.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR, FPU, priority grouping.
Postcondition
Control passes to the active app, or to the ThreadX-hosted DFU device.
On any HAL init failure the function halts in WFI.
Note
Single entry point; not re-entrant.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss; SystemInit ran.
The embedded image's first two words are a valid MSP + Thumb reset vector.
Postcondition
On success, control is at the image's reset vector in the SRAM run window.
On a failed run-target check, control parks in internal_dcr_panic_halt.
Note
Single entry point; not re-entrant.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler copied .data and zeroed .bss.
SystemInit set VTOR, FPU, priority grouping.
Postcondition
On clean entry the CPU stays in tx_kernel_enter forever.
On any HAL init failure the function halts in WFI.
Note
Single entry point; not re-entrant.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit enabled the MPU + caches via RA8_BOOT_ENABLE_CACHE_MPU.
Postcondition
Exactly one PASS/FAIL banner is emitted, then the core parks.
The core ends in WFI so ra8_emulator's idle-stop terminates the run.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Initializes the demo, executes one comparison per period, increments the exported match or mismatch counter, and toggles the matching LED.

Precondition
Reset startup and SystemInit completed successfully.
DOC and the status LEDs are not owned by another context.
Postcondition
Every iteration increments exactly one HIL result counter.
LED1 represents matches and LED2 represents failures or mismatches.
Note
Does not return during normal operation.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clock tree, MSTP, ISR/ELC, and the VCOM console, programs a software-triggered DTC block copy, runs it with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI.

Precondition
Reset_Handler has copied .data and zeroed .bss.
SystemInit enabled the MPU + caches via RA8_BOOT_ENABLE_CACHE_MPU.
Postcondition
Exactly one PASS/FAIL banner is emitted, then the core parks.
The core ends in WFI so ra8_emulator's idle-stop terminates the run.
Note
Single-threaded; the completion IRQ is left masked and the result polled.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, zeros the shared control block, releases the Cortex-M33, waits for its boot signature, then yields while the M33 counts autonomously to k_bg_target_count. After the M33 sets done, the M85 reads the counter and logs the PASS/FAIL verdict.

Precondition
SystemInit has completed core bring-up.
The M33 is held in reset by hardware until released here.
Postcondition
The M33 has autonomously incremented the counter and set done.
This function never returns to its caller.
Note
Single-threaded; no RTOS on the M85 in this example.
Since
0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, releases the Cortex-M33, confirms it booted, runs k_m85_demo_rounds narrated mailbox rounds, then drops into the idle heartbeat. See the file header for the teaching narrative.

Precondition
SystemInit has completed core bring-up.
The M33 is held in reset by hardware until released here.
Postcondition
The M33 has been released and the mailbox exchange is running.
This function never returns to its caller.
Note
Single-threaded; no RTOS on the M85 in this example.
Since
0.1.0

Definition at line 305 of file main.c.

References g_ecc_heartbeat, g_ecc_ok, internal_configure(), internal_panic_halt(), internal_sample(), internal_setup_or_halt(), k_ecc_demo_period_ms, k_ra8_board_led1, k_ra8_board_led2, k_ra8_ok, ra8_board_led_toggle(), ra8_board_uart_console_write(), ra8_delay_ms(), ra8_isr_globals_enable(), s_ecc_demo_bad_msg, and s_ecc_demo_ok_msg.

Variable Documentation

◆ g_ecc_1bit

volatile uint32_t g_ecc_1bit = 0U

Per-bank 1-bit-error bitmap from the last SRAMESR read (bit n = bank n).

Note
Read externally only. Meaningful on silicon; ra8_emulator does not model ECC.
Since
0.1.0

Definition at line 108 of file main.c.

Referenced by internal_sample().

◆ g_ecc_2bit

volatile uint32_t g_ecc_2bit = 0U

Per-bank 2-bit-error bitmap from the last SRAMESR read (bit n = bank n).

Note
Read externally only. Meaningful on silicon; ra8_emulator does not model ECC.
Since
0.1.0

Definition at line 116 of file main.c.

Referenced by internal_sample().

◆ g_ecc_esr

volatile uint32_t g_ecc_esr = 0U

Last raw SRAMESR snapshot (0 = no ECC error latched).

Note
Read externally only.
Since
0.1.0

Definition at line 100 of file main.c.

Referenced by internal_sample().

◆ g_ecc_heartbeat

volatile uint32_t g_ecc_heartbeat = 0U

Bumps once per main-loop pass – liveness for headless probes.

Note
Read externally only.
Since
0.1.0

Definition at line 124 of file main.c.

Referenced by main().

◆ g_ecc_ok

volatile uint32_t g_ecc_ok = 0U

1 when ECC is healthy: rw round-trips and no error is latched.

Note
Read externally only (HIL / board emulator).
Since
0.1.0

Definition at line 84 of file main.c.

Referenced by main().

◆ g_ecc_rw_ok

volatile uint32_t g_ecc_rw_ok = 0U

1 when the ECC-protected buffer read back exactly.

Note
Read externally only.
Since
0.1.0

Definition at line 92 of file main.c.

Referenced by internal_sample().

◆ s_ecc_buf

volatile uint32_t* s_ecc_buf = nullptr
static

Base of the ECC-protected bank, resolved at init.

Definition at line 127 of file main.c.

Referenced by internal_configure(), and internal_sample().

◆ s_ecc_demo_bad_msg

const uint8_t s_ecc_demo_bad_msg[] = "ecc: sram2 rw=BAD ok=N\r\n"
static

Definition at line 76 of file main.c.

Referenced by main().

◆ s_ecc_demo_ok_msg

const uint8_t s_ecc_demo_ok_msg[] = "ecc: sram2 ecc=on rw=ok ok=Y\r\n"
static

Output line tags.

Definition at line 75 of file main.c.

Referenced by main().

◆ s_tag

const char* s_tag = "ecc_demo"
static

Diagnostic / log tag.

Definition at line 59 of file main.c.