cpu1_main.c File Reference

CPU1 (Cortex-M33) ping-pong responder. More...

#include <stdint.h>
#include "ra8_err.h"
#include "shared_pingpong.h"

Include dependency graph for cpu1_main.c:

Go to the source code of this file.

Functions
void	cpu1_reset_handler (void)
	CPU1 reset handler.
static void	internal_cpu1_main (void)
	CPU1 application loop.
static void	internal_fault_handler (void)
	Default fault handler.

Variables
uint32_t	g_ra8_ls_cpu1_stack_top
uint32_t	g_ra8_ls_cpu1_data_start
uint32_t	g_ra8_ls_cpu1_data_end
uint32_t	g_ra8_ls_cpu1_data_load
uint32_t	g_ra8_ls_cpu1_bss_start
uint32_t	g_ra8_ls_cpu1_bss_end
const uintptr_t	g_cpu1_vector_table []

Detailed Description

CPU1 (Cortex-M33) ping-pong responder.

Tag

[Ring 1 / app] {World: NS}

Built as a separate ELF (-mcpu=cortex-m33). Polls the shared SRAM struct at 0x22100000 for a ping_seq advance; on each new ping writes the pong payload and acks via pong_seq. No IPC peripheral is used – see shared_pingpong.h for the rationale.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file cpu1_main.c.

Function Documentation

cpu1_reset_handler()

void cpu1_reset_handler

(

void

)

CPU1 reset handler.

Runs the minimal C-runtime init the M33 image needs before branching into internal_cpu1_main:

1. Copy .data from its MRAM_CPU1 load image into SRAM_CPU1.
2. Zero .bss in SRAM_CPU1.

Without these passes the CPU1 image's globals (e.g. the s_ipc_channels array in ra8_ipc.c – .bss – and any initialised file-scope statics – .data) hold whatever pattern SRAM_CPU1 contained at boot. That was the reason CPU1 silently stayed wedged after Agent D embedded the CPU1 binary: the M33 jumped straight into internal_cpu1_main with uninitialised globals, so ra8_ipc_init / ra8_ipc_recv_message operated on garbage state structures and the channel pair never came alive.

Precondition

Initial SP loaded by hardware from the first slot of .cpu1_vectors (= g_ra8_ls_cpu1_stack_top).

CPU1 has just exited reset via the ACTREQ handshake driven by ra8_cpu1_release on CPU0.

Postcondition

.data mirrors the MRAM_CPU1 load image.

.bss is zero-filled.

Never returns; internal_cpu1_main enters its infinite shared-SRAM loop.

Note

Called only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Definition at line 99 of file cpu1_main.c.

References g_ra8_ls_cpu1_bss_end, g_ra8_ls_cpu1_bss_start, g_ra8_ls_cpu1_data_end, g_ra8_ls_cpu1_data_load, g_ra8_ls_cpu1_data_start, and internal_cpu1_main().

internal_cpu1_main()

void internal_cpu1_main ( void )

static

CPU1 application loop.

See file header.

Precondition

Vector table installed.

The fixed shared-SRAM message block is reachable.

Postcondition

Loop never exits.

Each new ping sequence is acknowledged through pong_seq.

Note

Single-threaded entry.

Since

0.1.0

Definition at line 43 of file cpu1_main.c.

References internal_shared(), k_cpu1_pingpong_magic_ping, k_cpu1_pingpong_magic_pong, cpu1_pingpong_shared_t::ping_payload, cpu1_pingpong_shared_t::ping_seq, cpu1_pingpong_shared_t::pong_payload, cpu1_pingpong_shared_t::pong_seq, and RA8_INTERNAL.

internal_fault_handler()

void internal_fault_handler ( void )

static

Default fault handler.

All M33 exception slots route here.

Precondition

Hardware fault occurred.

Caller is the M33 exception entry path.

Postcondition

CPU1 stops making forward progress.

Watchdog (if enabled) eventually resets the chip.

Note

Used as default for all exception slots.

Since

0.1.0

Definition at line 130 of file cpu1_main.c.

References RA8_INTERNAL.

Variable Documentation

g_cpu1_vector_table

const uintptr_t g_cpu1_vector_table[]

Initial value:

                                     = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
}

Definition at line 149 of file cpu1_main.c.

g_ra8_ls_cpu1_bss_end

uint32_t g_ra8_ls_cpu1_bss_end

extern

g_ra8_ls_cpu1_bss_start

uint32_t g_ra8_ls_cpu1_bss_start

extern

g_ra8_ls_cpu1_data_end

uint32_t g_ra8_ls_cpu1_data_end

extern

g_ra8_ls_cpu1_data_load

uint32_t g_ra8_ls_cpu1_data_load

extern

g_ra8_ls_cpu1_data_start

uint32_t g_ra8_ls_cpu1_data_start

extern

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern