cpu1_main.c

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#include <stdint.h>
 
#include "ra8_err.h"
#include "shared_pingpong.h"
 
extern uint32_t g_ra8_ls_cpu1_stack_top;
extern uint32_t g_ra8_ls_cpu1_data_start;
extern uint32_t g_ra8_ls_cpu1_data_end;
extern uint32_t g_ra8_ls_cpu1_data_load;
extern uint32_t g_ra8_ls_cpu1_bss_start;
extern uint32_t g_ra8_ls_cpu1_bss_end;
 
[[noreturn]] void cpu1_reset_handler(void);

[[noreturn]] RA8_INTERNAL static void internal_cpu1_main(void)
{
  volatile cpu1_pingpong_shared_t* shared        = internal_shared();
  uint32_t                         last_observed = 0U;
 
  while (1) {
    /* Spin until CPU0 bumps the ping sequence. The reads are volatile,
     * so the compiler emits a fresh load each iteration. */
    while (shared->ping_seq == last_observed) {
      __asm volatile("nop");
    }
    last_observed = shared->ping_seq;
 
    /* Read the payload after the sequence advance so we know CPU0's
     * write of the payload preceded its sequence bump. */
    uint32_t got = shared->ping_payload;
    if (got != (uint32_t)k_cpu1_pingpong_magic_ping) {
      /* Wrong magic -- still ack so CPU0's poll doesn't block. CPU0
       * will count the mismatch via the payload check on its side. */
      shared->pong_payload = 0U;
    } else {
      shared->pong_payload = (uint32_t)k_cpu1_pingpong_magic_pong;
    }
    __asm volatile("dsb" ::: "memory");
    shared->pong_seq = last_observed;
  }
}

[[noreturn]] void cpu1_reset_handler(void)
{
  /* Copy .data from MRAM_CPU1 load address into SRAM_CPU1. The linker
   * defines ``g_ra8_ls_cpu1_data_load`` as LOADADDR(.data) so this
   * works regardless of the absolute MRAM_CPU1 base. */
  uint32_t* dst = &g_ra8_ls_cpu1_data_start;
  uint32_t* src = &g_ra8_ls_cpu1_data_load;
  while (dst < &g_ra8_ls_cpu1_data_end) {
    *dst = *src;
    dst++;
    src++;
  }
  /* Zero .bss in SRAM_CPU1. */
  uint32_t* bss = &g_ra8_ls_cpu1_bss_start;
  while (bss < &g_ra8_ls_cpu1_bss_end) {
    *bss = 0U;
    bss++;
  }
  internal_cpu1_main();
}

[[noreturn]] RA8_INTERNAL static void internal_fault_handler(void)
{
  while (1) {
    __asm volatile("nop");
  }
}

#ifndef RA8_OFF_TARGET
/* Vector table only built for the cross-compiled M33 image. The host
 * build does not link this TU as an executable -- it is compile-checked
 * only -- so we can drop the table without losing test coverage. */
[[gnu::used, gnu::section(".cpu1_vectors")]] const uintptr_t g_cpu1_vector_table[] = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
};
#endif