cpu1_main.c File Reference

CPU1 (Cortex-M33) cache-coherency responder. More...

#include <stdint.h>
#include "cache_coherency_shared.h"

Include dependency graph for cpu1_main.c:

Go to the source code of this file.

Functions
void	cpu1_reset_handler (void)
	CPU1 reset handler.
static void	internal_cpu1_main (void)
	CPU1 responder loop.
static void	internal_fault_handler (void)
	Default fault handler.

Variables
uint32_t	g_ra8_ls_cpu1_stack_top
uint32_t	g_ra8_ls_cpu1_data_start
uint32_t	g_ra8_ls_cpu1_data_end
uint32_t	g_ra8_ls_cpu1_data_load
uint32_t	g_ra8_ls_cpu1_bss_start
uint32_t	g_ra8_ls_cpu1_bss_end
const uintptr_t	g_cpu1_vector_table []

Detailed Description

CPU1 (Cortex-M33) cache-coherency responder.

Tag

[Ring 1 / app] {World: NS}

Built as a separate ELF (-mcpu=cortex-m33) and embedded into the M85 image by ra8_add_cpu1_image(). Polls the shared SRAM struct at 0x22100000 for a ping_seq advance; on each new ping it echoes the transformed payload (ping_payload + k_cache_coherency_delta) and acks via pong_seq. The Cortex-M33 has no data cache, so it always sees SRAM directly; the coherency burden is one-sided (the M85 D-cache), which the non-cacheable MPU region on the M85 side removes. No IPC peripheral is used – see cache_coherency_shared.h for the rationale.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file cpu1_main.c.

Function Documentation

cpu1_reset_handler()

void cpu1_reset_handler

(

void

)

CPU1 reset handler.

Runs the minimal C-runtime init the M33 image needs before branching into cpu1_main:

1. Copy .data from its MRAM_CPU1 load image into SRAM_CPU1.
2. Zero .bss in SRAM_CPU1.

Precondition

Initial SP loaded by hardware from the first slot of .cpu1_vectors (= g_ra8_ls_cpu1_stack_top).

CPU1 has just exited reset via the ACTREQ handshake driven by ra8_cpu1_release on CPU0.

Postcondition

.data mirrors the MRAM_CPU1 load image.

.bss is zero-filled.

Never returns; cpu1_main enters its responder loop.

Note

Called only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Definition at line 90 of file cpu1_main.c.

References g_ra8_ls_cpu1_bss_end, g_ra8_ls_cpu1_bss_start, g_ra8_ls_cpu1_data_end, g_ra8_ls_cpu1_data_load, g_ra8_ls_cpu1_data_start, and internal_cpu1_main().

internal_cpu1_main()

void internal_cpu1_main ( void )

static

CPU1 responder loop.

See file header. Each ping is echoed as ping_payload + delta so the M85 can verify the round-trip carried data end-to-end.

Precondition

Vector table installed.

Shared block reachable at k_cache_coherency_shared_addr.

Postcondition

Loop never exits.

pong_seq tracks ping_seq after each reply.

Note

Single-threaded entry.

Since

0.1.0

Definition at line 48 of file cpu1_main.c.

References internal_shared(), k_cache_coherency_delta, cache_coherency_shared_t::ping_payload, cache_coherency_shared_t::ping_seq, cache_coherency_shared_t::pong_payload, cache_coherency_shared_t::pong_seq, and RA8_INTERNAL.

internal_fault_handler()

void internal_fault_handler ( void )

static

Default fault handler.

All M33 exception slots route here.

Precondition

Hardware fault occurred.

Caller is the M33 exception entry path.

Postcondition

CPU1 stops making forward progress.

Watchdog (if enabled) eventually resets the chip.

Note

Used as default for all exception slots.

Since

0.1.0

Definition at line 119 of file cpu1_main.c.

References RA8_INTERNAL.

Variable Documentation

g_cpu1_vector_table

const uintptr_t g_cpu1_vector_table[]

Initial value:

                                     = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
  (uintptr_t)&internal_fault_handler,
}

Definition at line 138 of file cpu1_main.c.

g_ra8_ls_cpu1_bss_end

uint32_t g_ra8_ls_cpu1_bss_end

extern

g_ra8_ls_cpu1_bss_start

uint32_t g_ra8_ls_cpu1_bss_start

extern

g_ra8_ls_cpu1_data_end

uint32_t g_ra8_ls_cpu1_data_end

extern

g_ra8_ls_cpu1_data_load

uint32_t g_ra8_ls_cpu1_data_load

extern

g_ra8_ls_cpu1_data_start

uint32_t g_ra8_ls_cpu1_data_start

extern

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern