cpu1_main.c File Reference

CPU1 (Cortex-M33 secondary core) image: blink LED1 forever. More...

#include <stdint.h>

Include dependency graph for cpu1_main.c:

Go to the source code of this file.

Enumerations
enum	m33_port_addr_t : uintptr_t { k_port6_pcntr1_addr = 0x404000C0U }
	MMIO address of the PORT6 control register driving LED1. More...
enum	m33_blink_const_t : uint32_t {   k_led1_pdr_out = 0x00000001U ,   k_led1_podr_on = 0x00010000U ,   k_blink_spins = 3000000U }
	PCNTR1 bit fields for LED1 and the blink-loop delay bound. More...

Functions
void	cpu1_reset_handler (void)
	CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.
static void	cpu1_main (void)
	CPU1 application loop: blink LED1 (BLUE, P600) forever.
static void	cpu1_fault_handler (void)
	CPU1 default fault handler: park the core.

Variables
uint32_t	g_ra8_ls_cpu1_stack_top
	CPU1 stack top (slot 0 of the M33 vector table).
uint32_t	g_ra8_ls_cpu1_data_start
	CPU1 .data run-region start (in SRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_data_end
	CPU1 .data run-region end.
uint32_t	g_ra8_ls_cpu1_data_load
	CPU1 .data load image (in MRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_bss_start
	CPU1 .bss start (in SRAM_CPU1).
uint32_t	g_ra8_ls_cpu1_bss_end
	CPU1 .bss end.
const uintptr_t	g_cpu1_vector_table []

Detailed Description

CPU1 (Cortex-M33 secondary core) image: blink LED1 forever.

Tag

[Ring 1 / app] {World: NS}

This is the firmware that runs on the RA8D2's second core, the Cortex-M33. It is compiled as a wholly separate ELF (-mcpu=cortex-m33) and embedded into the M85 ELF as a .cpu1_image blob; the M85 releases this core at runtime via ra8_cpu1_release (HUM Ch 2.9.1 "CPU control registers"), then sleeps.

Its job is intentionally tiny so the dual-core plumbing is what stands out: it drives board LED1 (BLUE, P600 = PORT6 pin 0) high and low forever with a bounded busy-delay between toggles. A blinking LED that the M85 never touches is honest proof the M33 came out of reset and is executing its own code – on silicon and in the ra8_emulator GPIO/LED view alike.

Note

The M33 deliberately does NOT call ra8_log. On hardware each core has its own CoreSight ITM and the ra8_emulator echoes only the primary core's ITM, so an M33 ra8_log line would be invisible in the fake. The proof-of-life is the LED transition the M85 never drives.

Only PCNTR1 is touched (direction + output level); the LED pins power up routed to PORT, so no PmnPFS / PWPR pin-function setup is needed here.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file cpu1_main.c.

Enumeration Type Documentation

m33_blink_const_t

enum m33_blink_const_t : uint32_t

PCNTR1 bit fields for LED1 and the blink-loop delay bound.

PCNTR1 packs the direction latch PDR in its low half and the output latch PODR in its high half, so pin 0 is held an output (PDR bit 0) while its level is set by PODR bit 0 (bit 16 of the word).

Since

0.1.0

Enumerator
k_led1_pdr_out	PCNTR1 PDR pin 0 = output direction.
k_led1_podr_on	PCNTR1 PODR pin 0 = drive high (bit 16).
k_blink_spins	Bounded busy-delay spins per LED half-cycle.

Definition at line 69 of file cpu1_main.c.

m33_port_addr_t

enum m33_port_addr_t : uintptr_t

MMIO address of the PORT6 control register driving LED1.

The EK-RA8D2 LED1 (BLUE) is P600 = PORT6 pin 0. The PORT block base is 0x40400000 with a 0x20 per-port stride, so PORT6 PCNTR1 lives at 0x40400000 + 6 * 0x20 = 0x404000C0 (HUM Ch 20 "I/O Ports").

Since

0.1.0

Enumerator
k_port6_pcntr1_addr	PORT6 PCNTR1: {PODR[31:16], PDR[15:0]}.

Definition at line 57 of file cpu1_main.c.

Function Documentation

cpu1_fault_handler()

void cpu1_fault_handler ( void )

static

CPU1 default fault handler: park the core.

Every M33 exception slot routes here. The core stops making forward progress; on hardware a watchdog (if enabled) eventually resets.

Returns

This function never returns.

Note

The core spins in place.

Precondition

A hardware fault or unhandled exception occurred.

Entered via the M33 exception entry path.

Postcondition

The M33 makes no further forward progress.

The LED stops toggling, which is observable from the M85.

Note

Shared default for all CPU1 exception vectors.

Since

0.1.0

Definition at line 168 of file cpu1_main.c.

cpu1_main()

void cpu1_main ( void )

static

CPU1 application loop: blink LED1 (BLUE, P600) forever.

Holds PORT6 pin 0 an output via PCNTR1.PDR and toggles its PODR level on each pass, with a bounded busy-delay between toggles so the blink is visible. The M85 never writes this pin, so the transitions prove the M33 is running. See the file header.

Returns

This function never returns.

Note

Control never leaves the blink loop.

Precondition

cpu1_reset_handler has initialised .data/.bss.

The PORT6 block is reachable at k_port6_pcntr1_addr.

Postcondition

PORT6 pin 0 is configured as an output.

The LED1 level alternates on the configured cadence forever.

Note

Single-threaded; runs in M33 thread mode with no RTOS.

Since

0.1.0

Definition at line 94 of file cpu1_main.c.

References k_blink_spins, k_led1_pdr_out, k_led1_podr_on, and k_port6_pcntr1_addr.

cpu1_reset_handler()

void cpu1_reset_handler

(

void

)

CPU1 reset handler: minimal C-runtime init, then enter cpu1_main.

The M33 boots with uninitialised RAM, so before any C code runs this copies .data from its MRAM_CPU1 load image into SRAM_CPU1 and zeroes .bss. The linker exports the region bounds as g_ra8_ls_cpu1_* symbols.

Returns

This function never returns.

Note

Control passes to cpu1_main, which loops forever.

Precondition

Hardware loaded the initial SP from .cpu1_vectors[0].

The M85 released this core via the CPU1ACTCSR handshake.

Postcondition

.data mirrors its MRAM_CPU1 load image.

.bss is zero-filled.

Note

Entered only from the CPU1 vector table; runs in M33 thread mode.

Since

0.1.0

Definition at line 132 of file cpu1_main.c.

References cpu1_main(), g_ra8_ls_cpu1_bss_end, g_ra8_ls_cpu1_bss_start, g_ra8_ls_cpu1_data_end, g_ra8_ls_cpu1_data_load, and g_ra8_ls_cpu1_data_start.

Variable Documentation

g_cpu1_vector_table

const uintptr_t g_cpu1_vector_table[]

Initial value:

                                     = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
}

Definition at line 189 of file cpu1_main.c.

g_ra8_ls_cpu1_bss_end

uint32_t g_ra8_ls_cpu1_bss_end

extern

CPU1 .bss end.

g_ra8_ls_cpu1_bss_start

uint32_t g_ra8_ls_cpu1_bss_start

extern

CPU1 .bss start (in SRAM_CPU1).

g_ra8_ls_cpu1_data_end

uint32_t g_ra8_ls_cpu1_data_end

extern

CPU1 .data run-region end.

g_ra8_ls_cpu1_data_load

uint32_t g_ra8_ls_cpu1_data_load

extern

CPU1 .data load image (in MRAM_CPU1).

g_ra8_ls_cpu1_data_start

uint32_t g_ra8_ls_cpu1_data_start

extern

CPU1 .data run-region start (in SRAM_CPU1).

g_ra8_ls_cpu1_stack_top

uint32_t g_ra8_ls_cpu1_stack_top

extern

CPU1 stack top (slot 0 of the M33 vector table).