cpu1_main.c

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#include <stdint.h>
 
#include "lowpower_holdpage.h"

extern uint32_t g_ra8_ls_cpu1_stack_top;
extern uint32_t g_ra8_ls_cpu1_data_start;
extern uint32_t g_ra8_ls_cpu1_data_end;
extern uint32_t g_ra8_ls_cpu1_data_load;
extern uint32_t g_ra8_ls_cpu1_bss_start;
extern uint32_t g_ra8_ls_cpu1_bss_end;
 
[[noreturn]] void cpu1_reset_handler(void);

typedef enum : uintptr_t {
  k_port6_pcntr1_addr = 0x404000C0U, 
  k_port0_pcntr2_addr = 0x40400004U, 
} m33_port_addr_t;

typedef enum : uint32_t {
  k_led1_pdr_out = 0x00000001U, 
  k_led1_podr_on = 0x00010000U, 
  k_sw1_pidr_bit = 9U,          
  k_sw1_released = 1U,          
  k_sw1_pressed  = 0U,          
  k_hold_spins   = 3000000U,    
} m33_hold_const_t;

[[noreturn]] static void cpu1_hold_page(void)
{
  volatile lowpower_mailbox_t* mb       = lowpower_mailbox();
  volatile uint32_t*           pcntr1   = (volatile uint32_t*)k_port6_pcntr1_addr;
  volatile uint32_t*           pcntr2   = (volatile uint32_t*)k_port0_pcntr2_addr;
  uint32_t                     led      = 0U;
  uint32_t                     sw1_prev = (uint32_t)k_sw1_released;
 
  while (1) {
    for (volatile uint32_t d = 0U; d < (uint32_t)k_hold_spins; d++) {
      __asm volatile("nop");
    }
    mb->m33_heartbeat = mb->m33_heartbeat + 1U;
 
    /* HUM Ch 20.2 "PCNTR2 : Port Control Register 2" p 841 -- read PIDR; bit 9
     * is SW1 (P009), active-low (pressed = 0). */
    const uint32_t pidr    = *pcntr2;
    const uint32_t sw1_now = (pidr >> (uint32_t)k_sw1_pidr_bit) & 1U;
    /* Detect a fresh press edge (was released, now pressed): a held-page turn
     * the slow core handles without waking the M85. Split conditions to avoid a
     * compound boolean decision. */
    if (sw1_prev == (uint32_t)k_sw1_released) {
      if (sw1_now == (uint32_t)k_sw1_pressed) {
        mb->sw1_events = mb->sw1_events + 1U;
        mb->page_num   = mb->page_num + 1U;
      }
    }
    sw1_prev = sw1_now;
 
    /* Toggle LED1 as the "active core = M33" indicator. */
    led ^= 1U;
    uint32_t value = (uint32_t)k_led1_pdr_out;
    if (led != 0U) {
      value |= (uint32_t)k_led1_podr_on;
    }
    /* HUM Ch 20.2 "PCNTR1 : Port Control Register 1" p 840 -- write {PODR, PDR}:
     * hold PORT6 pin 0 an output and drive LED1 (BLUE, P600) to the new level. */
    *pcntr1 = value;
  }
}

[[noreturn]] void cpu1_reset_handler(void)
{
  uint32_t* dst = &g_ra8_ls_cpu1_data_start;
  uint32_t* src = &g_ra8_ls_cpu1_data_load;
  while (dst < &g_ra8_ls_cpu1_data_end) {
    *dst = *src;
    dst++;
    src++;
  }
 
  uint32_t* bss = &g_ra8_ls_cpu1_bss_start;
  while (bss < &g_ra8_ls_cpu1_bss_end) {
    *bss = 0U;
    bss++;
  }
 
  cpu1_hold_page();
}

[[noreturn]] static void cpu1_fault_handler(void)
{
  while (1) {
    __asm volatile("nop");
  }
}

#ifndef RA8_OFF_TARGET
/* The vector table is only meaningful in the cross-compiled M33 image. The host
 * unit-test build compile-checks this TU but never links it as an executable, so
 * dropping the table there costs no coverage. */
[[gnu::used, gnu::section(".cpu1_vectors")]] const uintptr_t g_cpu1_vector_table[] = {
  (uintptr_t)&g_ra8_ls_cpu1_stack_top,
  (uintptr_t)&cpu1_reset_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
  (uintptr_t)&cpu1_fault_handler,
};
#endif