Shared-SRAM contract for the low-power "hold the page" dual-core demo. More...

#include <stdint.h>
#include "ra8_board_ek_ra8d2_dualcore.h"

Include dependency graph for lowpower_holdpage.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	lowpower_mailbox_t
	Cross-core handoff block backed by a fixed shared-SRAM address. More...

Enumerations
enum	lowpower_mailbox_addr_t : uintptr_t { k_lowpower_mailbox_addr }
	Fixed shared-SRAM base address of the mailbox. More...
enum	lowpower_const_t : uint32_t { k_lowpower_magic = 0x484F4C44U , k_lowpower_core_m85 = 0U , k_lowpower_core_m33 = 1U }
	Signature + active-core enumerators shared by both core images. More...

Functions
static volatile lowpower_mailbox_t *	lowpower_mailbox (void)
	Typed pointer to the fixed-address shared mailbox.

Detailed Description

Shared-SRAM contract for the low-power "hold the page" dual-core demo.

Tag: [Ring 6 / APP] {World: S}

This header pins the cross-core message block for the #150 low-power-mode demo at one fixed shared-SRAM address both core images agree on. The Cortex-M85 (primary, "CPU0") renders a page, hands the workload to the Cortex-M33 (secondary, "CPU1"), and parks; the M33 then HOLDS the page and services the user switch at a fraction of the power. The mailbox carries the handoff state both directions.

Why a fixed address: each core is a separate compiled image with its own linker script, so a static global in one image is invisible to the other. Both linker scripts leave SRAM2 (which starts at 0x22100000) unclaimed – the M85 image uses SRAM0+SRAM1 (ending at 0x22100000) and the M33 image uses a separate 64 KiB block – so the bytes at 0x22100000 are backed by the same physical SRAM on both sides with no overlap.

Coherency: this app's system_init.c leaves the M85 data cache OFF, so a store from one core is visible to the other once a dsb has drained the write buffer; no cache clean / invalidate dance is needed. The fields are volatile so the compiler emits a real load/store on every access.

Protocol (the low-power handoff):

M85 renders page 0 (a page marker stands in for a GLCDC render here), writes page_num, sets active_core = M33, stamps magic, dsb.
M85 releases the M33 and PARKS (WFI). The M33 owns the page now.
M33 holds the page: bumps m33_heartbeat each loop, lights the "active core = M33" LED, and on a SW1 (P009) press edge bumps sw1_events and advances page_num (a held-page page-turn the slow core can do without waking the M85). Waking the M85 for a heavy re-render is the remaining piece tracked in #150.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file lowpower_holdpage.h.

Enumeration Type Documentation

◆ lowpower_const_t

enum lowpower_const_t : uint32_t

Signature + active-core enumerators shared by both core images.

k_lowpower_magic ("HOLD") lets each core confirm the mailbox is live before trusting its fields; active_core names which core currently owns the page – the whole point of the demo is that it flips from M85 to M33 when low-power mode engages.

See also: lowpower_mailbox_t

Since: 0.1.0

Enumerator
k_lowpower_magic	"HOLD" – M85 stamps it when ready.
k_lowpower_core_m85	active_core: the M85 owns the page.
k_lowpower_core_m33	active_core: the M33 holds the page.

Definition at line 84 of file lowpower_holdpage.h.

◆ lowpower_mailbox_addr_t

enum lowpower_mailbox_addr_t : uintptr_t

Fixed shared-SRAM base address of the mailbox.

The mailbox sits at the base of the CPU0 <-> CPU1 window. The window itself is a board fact, declared once in ra8_board_ek_ra8d2_dualcore.h along with why both linker scripts leave it free; this app only names its own slice of it.

Invariant: The address is 16-byte aligned (cache-line safe).

See also: ra8_board_dualcore_addr_t; lowpower_mailbox()

Since: 0.1.0

Enumerator
k_lowpower_mailbox_addr	Mailbox base = window base.

Definition at line 67 of file lowpower_holdpage.h.

Function Documentation

◆ lowpower_mailbox()

volatile lowpower_mailbox_t * lowpower_mailbox ( void )

inlinestatic

Typed pointer to the fixed-address shared mailbox.

Inlined so both core images compute the identical address with no shared translation unit. Returns the same physical SRAM location on the M85 and the M33.

Returns: Pointer to the mailbox at k_lowpower_mailbox_addr.

Return values

non-NULL Always; the address is a compile-time constant.

Precondition: The linker scripts of both images leave SRAM2 unallocated.; The M85 data cache is disabled (see file header).

Postcondition: Returns a valid volatile pointer; never NULL.; No side effects.

Note: Callable from either core; the pointer arithmetic is identical.

Since: 0.1.0

Definition at line 142 of file lowpower_holdpage.h.

References k_lowpower_mailbox_addr.

Referenced by cpu1_hold_page(), and main().

Data Structures